参数资料
| 型号： | NCP5386MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 24/33页 |
| 文件大小： | 0K |
| 描述： | IC CTLR BUCK 1/2PHASE 32-QFN |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel VR10、VR11、AMD CPU |
| 输入电压： | 4.75 V ~ 5.25 V |
| 输出数： | 2 |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 带卷 (TR) |
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NCP5386, NCP5386A, NCP5386B
PWM Comparators with Hysteresis
Four PWM comparators receive the error amplifier
output signal at their noninverting input. Each comparator
receives one of the triangle waves offset by 1.3 V at it’s
inverting input. The output of the comparator generates the
PWM outputs G1 and G2.
During steady state operation, the duty cycle will center
on the valley of the triangle waveform, with steady state
duty cycle calculated by V OUT /V IN . During a transient
event, both high and low comparator output transitions
shift phase to the points where the error amplifier output
intersects the down and up ramp of the triangle wave.
PROTECTION FEATURES
Undervoltage Lockout
An undervoltage lockout (UVLO) senses the V CC input.
During powerup, the input voltage to the controller is
monitored, and the PWM outputs and the soft ? start circuit
are disabled until the input voltage exceeds the threshold
voltage of the UVLO comparator. The UVLO comparator
incorporates hysteresis to avoid chattering, since V CC is
likely to decrease as soon as the converter initiates
soft ? start.
Overcurrent Shutdown
A programmable overcurrent function is incorporated
within the IC. A comparator and latch makeup this
function. The inverting input of the comparator is
connected to the ILIM pin. The voltage at this pin sets the
maximum output current the converter can produce. The
ROSC pin provides a convenient and accurate reference
voltage from which a resistor divider can create the
overcurrent setpoint voltage. Although not actually
disabled, tying the ILIM pin directly to the ROSC pin sets
the limit above useful levels – effectively disabling
overcurrent shutdown. The comparator noninverting input
is the summed current information from the current sense
amplifiers. The overcurrent latch is set when the current
information exceeds the voltage at the ILIM pin. The
outputs are immediately disabled, the VR_RDY and
DRVON pins are pulled low, and the soft ? start is pulled
low. The outputs will remain disabled until the V CC voltage
is removed and re ? applied, or the ENABLE input is
brought low and then high.
Overvoltage Protection and Power Good Monitor
An output voltage monitor is incorporated. During
normal operation, if the voltage at the DIFFOUT pin
exceeds 1.3 V, the VR_RDY pin goes low, the DRVON
signal remains high, the PWM outputs are set low. The
outputs will remain disabled until the V CC voltage is
removed and reapplied. During normal operation, if the
output voltage falls more than 300 mV below the DAC
setting, the VR_RDY pin will be set low until the output
rises.
Soft ? Start
The NCP5386 incorporates an externally programmable
soft ? start. The soft ? start circuit works by controlling the
ramp ? up of the DAC voltage during powerup. The initial
soft ? start pin voltage is 0 V. The soft ? start circuitry clamps
the DAC input of the Remote Sense Amplifier to the SS pin
voltage until the SS pin voltage exceeds the DAC setting
minus VID offset thereafter. The soft ? start pin is pulled to
0 V.
There are two possible soft ? start modes: AMD and
VR11. AMD mode simply ramps Vcore from 0 V
directly to the DAC setting at the rate set by the capacitor
connected to the SS pin. The VR11 mode ramps Vcore to
1.1 V at the SS capacitor charge rate, pauses at 1.1 V for
170 m s, reads the VID pins to determine the DAC setting,
then ramps Vcore to the final DAC setting at the
Dynamic VID slew rate of 7.3 mV/ m s. Typical AMD and
VR11 soft ? start sequences are shown in the following
graphs.
?
1.3 V
+
REMOTE
SENSE
+ AMP
?
ERROR
AMP
VS ?
VS+
DIFFOUT
R1
V FB
C1
COMP
10 k
Figure 20. DAC Servo Evaluation Circuit
http://onsemi.com
24
1 nF
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