参数资料
| 型号： | NCP5386MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 30/33页 |
| 文件大小： | 0K |
| 描述： | IC CTLR BUCK 1/2PHASE 32-QFN |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel VR10、VR11、AMD CPU |
| 输入电压： | 4.75 V ~ 5.25 V |
| 输出数： | 2 |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 带卷 (TR) |
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NCP5386, NCP5386A, NCP5386B
A complex switching model is available by request
which includes a more detailed board parasitic for this
demo board.
Compensation and Output Filter Design
The values shown on the demo board are a good place to
start for any similar output filter solution. The dynamic
performance can then be adjusted by swapping out various
individual components.
If the required output filter and switching frequency are
significantly different, it’s best to use the available PSPICE
models to design the compensation and output filter from
scratch.
The design target for this demo board was 1.0 m W out to
2.0 MHz. The phase switching frequency is currently set to
330 kHz. It can easily be seen that the board impedance of
0.75 m W between the load and the bulk capacitance has a
large effect on the output filter. In this case the ten 560 m F
80
bulk capacitors have an ESR of 7.0 m W . Thus the bulk ESR
plus the board impedance is 0.7 m W + 0.75 m W or
1.45 m W . The actual output filter impedance does not drop
to 1.0 m W until the ceramic breaks in at over 375 kHz. The
controller must provide some loop gain slightly less than
one out to a frequency in excess 300 kHz. At frequencies
below where the bulk capacitance ESR breaks with the
bulk capacitance, the DC ? DC converter must have
sufficiently high gain to control the output impedance
completely. Standard Type ? 3 compensation works well
with the NCP5386. RFB1 should be kept above 50 W for
amplifier stability reasons.
The goal is to compensate the system such that the
resulting gain generates constant output impedance from
DC up to the frequency where the ceramic takes over
holding the impedance below 1.0 m W . See the example of
the locations of the poles and zeros that were set to optimize
the model above.
Zout Open Loop
Zout Closed Loop
Open Loop Gain with Current loop Closed
Voltage Loop Compensation Gain
1/(2*PI*RF*CH)
Error Amp
60
40
20
0
? 20
? 40
? 60
? 80
? 100
RF/RFB
1/(2*PI*CFB1*(RFB1+RFB))
1/(2*PI*CF*RF)
RF/RFB1
Open Loop
Gain
1/(2*PI*(RBRD+ESRBulk)*CBulk)
1/(2*PI*SQRT(ESL_Cer*CCer))
1mOhm
1/(2*PI*CCer*(RBRD+ESRBulk))
100
1000
10000
100000
1000000
10000000
Frequency
Figure 33.
By matching the following equations a good set of starting compensation values can be found for a typical mixed bulk
and ceramic capacitor type output filter.
+
+
1 1
2 p · CF · RF 2 p · (RBRD ) ESRBulk) · CBulk
1 1
2 p · CFBI · (RFBI ) RFB) 2 p · CCer * (RBRD ) ESRBulk)
http://onsemi.com
30
(eq. 9)
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