参数资料
| 型号： | NCP5386MNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 32/33页 |
| 文件大小： | 0K |
| 描述： | IC CTLR BUCK 1/2PHASE 32-QFN |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel VR10、VR11、AMD CPU |
| 输入电压： | 4.75 V ~ 5.25 V |
| 输出数： | 2 |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 带卷 (TR) |
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NCP5386, NCP5386A, NCP5386B
Ratio NTC curve, at the respective activation and
deactivation temperature.
Figure 35.
OVP
The overvoltage protection threshold is not adjustable.
OVP protection is enabled as soon as soft ? start begins and
is disabled when the part is disabled. When OVP is tripped,
the controller commands all two gate drivers to enable their
low side MOSFETs, and VR_RDY transitions low. In order
UVLO threshold. See the state diagram for further details.
The OVP circuit monitors the output of DIFFOUT. If the
DIFFOUT signal reaches 180 mV above the nominal 1.3 V
offset the OVP will trip. The DIFFOUT signal is the
difference between the output voltage and the DAC voltage
plus the 1.3 V internal offset. This results in the OVP
tracking the DAC voltage even during a dynamic change
in the VID setting during operation.
Gate Driver and MOSFET Selection
ON Semiconductor provides the companion gate driver
IC (NCP3418B). The NCP3418B driver is optimized to
work with a range of MOSFETs commonly used in CPU
applications. The NCP3418B provides special
functionality and is required for the high performance
dynamic VID operation of the part. Contact your local
ON Semiconductor applications engineer for
MOSFET recommendations.
Board Stackup
The demo board follows the recommended Intel Stackup
and copper thickness as shown.
to recover from an OVP condition, V CC must fall below the
Figure 36.
Board Layout
A complete Allegro ATX and BTX demo board layout
file and schematics are available by request at
www.onsemi.com and can be viewed using the Allegro
Free Physical Viewer 15.x from the Cadence website
Close attention should be paid to the routing of the sense
traces and control lines that propagate away from the
controller IC. Routing should follow the demo board
example. For further information or layout review contact
ON Semiconductor.
http://www.cadence.com/.
http://onsemi.com
32
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