参数资料
型号: C8051F300-GMR
厂商: Silicon Laboratories Inc
文件页数: 23/178页
文件大小: 0K
描述: IC 8051 MCU 8K FLASH 11QFN
产品培训模块: Serial Communication Overview
标准包装: 1,500
系列: C8051F30x
核心处理器: 8051
芯体尺寸: 8-位
速度: 25MHz
连通性: SMBus(2 线/I²C),UART/USART
外围设备: POR,PWM,温度传感器,WDT
输入/输出数: 8
程序存储器容量: 8KB(8K x 8)
程序存储器类型: 闪存
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 3.6 V
数据转换器: A/D 8x8b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 10-VFDFN 裸露焊盘
包装: 带卷 (TR)
配用: 336-1444-ND - ADAPTER PROGRAM TOOLSTICK F300
336-1351-ND - KIT REF DES TEMP COMPENS RTC
336-1348-ND - KIT STARTER TOOLSTICK
336-1283-ND - KIT REF DESIGN DTMF DECODER
336-1278-ND - KIT TOOL EVAL SYS IN A USB STICK
336-1246-ND - DEV KIT F300/301/302/303/304/305
Rev. 2.9
119
C8051F300/1/2/3/4/5
13.4.2. SMB0CN Control Register
SMB0CN is used to control the interface and to provide status information (see SFR Definition 13.2). The
higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to
jump to service routines. MASTER and TXMODE indicate the master/slave state and transmit/receive
modes, respectively.
The STA bit indicates that a START has been detected or generated since the last SMBus interrupt. When
set to ‘1’, the STA bit will cause the SMBus to enter Master mode and generate a START when the bus
becomes free. STA is not cleared by hardware after the START is generated; it must be cleared by soft-
ware.
As a master, writing the STO bit will cause the hardware to generate a STOP condition and end the current
transfer after the next ACK cycle. STO is cleared by hardware after the STOP condition is generated. As a
slave, STO indicates that a STOP condition has been detected since the last SMBus interrupt. STO is also
used in slave mode to manage the transition from slave receiver to slave transmitter; see Section 13.5.4
for details on this procedure.
If STO and STA are both set to ‘1’ (while in Master Mode), a STOP followed by a START will be generated.
As a receiver, writing the ACK bit defines the outgoing ACK value; as a transmitter, reading the ACK bit
indicates the value received on the last ACK cycle. ACKRQ is set each time a byte is received, indicating
that an outgoing ACK value is needed. When ACKRQ is set, software should write the desired outgoing
value to the ACK bit before clearing SI. A NACK will be generated if software does not write the ACK bit
before clearing SI. SDA will reflect the defined ACK value immediately following a write to the ACK bit;
however SCL will remain low until SI is cleared. If a received slave address is not acknowledged, further
slave events will be ignored until the next START is detected.
The ARBLOST bit indicates that the interface has lost an arbitration. This may occur anytime the interface
is transmitting (master or slave). A lost arbitration while operating as a slave indicates a bus error condi-
tion. ARBLOST is cleared by hardware each time SI is cleared.
The SI bit (SMBus Interrupt Flag) is set at the beginning and end of each transfer, after each byte frame, or
when an arbitration is lost; see Table 13.3 for more details.
Important Note About the SI Bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and
the bus is stalled until software clears SI.
Table 13.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 13.4 for SMBus sta-
tus decoding using the SMB0CN register.
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