参数资料
型号: C8051F302-GS
厂商: Silicon Laboratories Inc
文件页数: 29/178页
文件大小: 0K
描述: IC 8051 MCU 8K FLASH 14-SOIC
产品培训模块: Serial Communication Overview
标准包装: 56
系列: C8051F30x
核心处理器: 8051
芯体尺寸: 8-位
速度: 25MHz
连通性: SMBus(2 线/I²C),UART/USART
外围设备: POR,PWM,温度传感器,WDT
输入/输出数: 8
程序存储器容量: 8KB(8K x 8)
程序存储器类型: 闪存
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 3.6 V
数据转换器: A/D 8x8b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 14-SOIC(0.154",3.90mm 宽)
包装: 管件
产品目录页面: 622 (CN2011-ZH PDF)
配用: 336-1444-ND - ADAPTER PROGRAM TOOLSTICK F300
其它名称: 336-1537-5
C8051F300/1/2/3/4/5
124
Rev. 2.9
13.5.2. Master Receiver Mode
Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the
START condition and transmits the first byte containing the address of the target slave and the data direc-
tion bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then received from the
slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more bytes of serial
data. After each byte is received, ACKRQ is set to ‘1’ and an interrupt is generated. Software must write
the ACK bit (SMB0CN.1) to define the outgoing acknowledge value (Note: writing a ‘1’ to the ACK bit gen-
erates an ACK; writing a ‘0’ generates a NACK). Software should write a ‘0’ to the ACK bit after the last
byte is received, to transmit a NACK. The interface exits Master Receiver Mode after the STO bit is set and
a STOP is generated. Note that the interface will switch to Master Transmitter Mode if SMB0DAT is written
while an active Master Receiver. Figure 13.6 shows a typical Master Receiver sequence. Two received
data bytes are shown, though any number of bytes may be received. Notice that the ‘data byte transferred’
interrupts occur before the ACK cycle in this mode.
Data Byte
A
N
A
S
R
P
SLA
S = START
P = STOP
A = ACK
N = NACK
R = READ
SLA = Slave Address
Received by SMBus
Interface
Transmitted by
SMBus Interface
Interrupt
Figure 13.6. Typical Master Receiver Sequence
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