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参数资料
| 型号： | C9821GQ |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | 单时钟驱动器| SSOP封装| 24针|塑料 |
| 文件页数： | 6/18页 |
| 文件大小： | 121K |
| 代理商： | C9821GQ |
Direct Rambus
Plus Clock Generator
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07092 Rev. **
05/03/2001
Page 6 of 18
APPROVED PRODUCT
C9821
Selection Logic (Cont.)
Table 2 shows the logic for selecting the PLL prescaler and feedback dividers to determine the multiply ratio for the
PLL from the input Refclk. Divider A sets the feedback and Divider B sets the prescaler, so the PLL output is set by:
PLLclk = Refclk*A/B.
Mode
Normal
Clk Stop
StopB
1
0
Clk
PAclk
V
X,STOP
ClkB
PAclkB
V
X,STOP
Table 3: Clk Stop Mode Selection
Table 3 shows the logic for enabling the clock outputs, using the StopB input signal. When StopB is high, the DRCG
is in its normal mode, and Clk and ClkB are complementary outputs following the Phase Aligner output (PAclk).
When StopB is low, the DRCG is in the Clk Stop mode, the output drivers are both disabled (set to Hi-Z), and the Clk
and ClkB outputs both drive DC voltages (V
X,STOP
) as given in Table 11. The level of V
X,STOP
is set by internal resistor
dividers.
Mode
Normal
Bypass
Test
Vendor Test A
Vendor Test B
Reserved
Output Test (OE)
S0
0
1
1
0
1
1
0
S1
0
0
1
0
0
1
1
S2
0
0
0
1
1
1
X
Bypclk (Int.)
Gnd
PLLclk
Refclk
-
-
-
-
Clk
PAclk
PLLclk
Refclk
-
-
-
Hi-Z
ClkB
PAclkB
PLLclkB
RefclkB
-
-
-
Hi-Z
Table 4: Bypass and Test Mode Selection
Power Management Functions
Mode
Normal
PowerDown
PwrDnB
1
0
Clk
PAclk
Gnd
ClkB
PAclkB
Gnd
Table 5: Powerdown Mode Selection
Table 5 shows the logic for selecting the Powerdown mode, using the PwrDnB input signal. PwrDnB is active low
(enabled when 0). When PwrDnB is disabled, the DRCG is in its normal mode. When PwrDnB is enabled, the DRCG
is put into a powered-off state, and the Clk and ClkB outputs are both low (ground).
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