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| 型号： | C9827JY |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | CPU系统时钟发生器| SSOP封装| 56PIN |塑料 |
| 文件页数： | 10/25页 |
| 文件大小： | 170K |
| 代理商： | C9827JY |
C9827J
High Performance Pentium 4 Clock Synthesizer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07107 Rev. **
5/24/2001
Page 10 of 25
Maximum Lumped Capacitive Output
Loads
Clock
Max Load
30
30
30
20
10
50
Table 5
Units
pF
pF
pF
pF
pF
pF
PCI Clocks
3V66 (0,1)
66B(0:2)
48MUSB Clock
48MDOT
REF Clock
Maximum Ratings
Input Voltage Relative to VSS:
Input Voltage Relative to VDDQ or AVDD: VDD+0.3V
Storage Temperature:
Operating Temperature:
Maximum Power Supply:
VSS-0.3V
-65
°
C to + 150
°
C
0
°
C to +85
°
C
3.5V
Test and Measurement Setup
For Differential CPU Output Signals
The following diagram shows lumped test load configurations for the differential Host Clock Outputs.
CLK Measurement Point
R
ref
R
tA1
CLK
CLK#
Mult0
CLK Measurement Point
R
LA1
R
D
R
LB1
R
LA2
R
LB2
R
tA2
R
tB1
R
tB2
C
LA
C
LB
T
PCB
T
PCB
Figure 1.
Lumped Test Load Configuration
1.0 Volt Amplitude Value
Component
R
tA1
, R
tA2
R
LA1
, R
LA2
T
PCB
R
LB1
, R
LB2
R
D
R
tB1
, R
tB2
C
LA
, C
LB
R
ref
0.7 Volt Amplitude Value
33
49.9
3” 50
Z
∞
∞
0
2pF
475
w/mult0=1
0
∞
3” 50
Z
63
470
33
2 pF
221
w/mult0=0
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