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| 型号： | C9832HY |
| 英文描述： | N-CHANNEL 60V - 0.014 Ohm - 60A TO-220/TO220FP STRIPFET POWER MOSFET |
| 中文描述： | CPU系统时钟发生器| SSOP封装| 56PIN |塑料 |
| 文件页数： | 14/24页 |
| 文件大小： | 169K |
| 代理商： | C9832HY |
C9832H
High Performance Pentium 4 Clock Synthesizer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07109 Rev. **
5/24/2001
Page 14 of 24
Approved Product
3V66 Buffered to PCI Buffered Clock Skew
The following figure shows the difference (skew) between the 3V33(0:1) outputs when 33M and 66M clocks are
connected to 66IN. This offset is described in the Group Timing Relationship and Tolerances section of this data
sheet. The measurements were taken at 1.5 volts.
3V66(0:1)
33M PCI
1.5-
3.5ns
3V66_(0:1) to PCI (0:6) and PCIF(0:2) Clock Skew Figure
Special Functions
PCI_F and IOAPIC Clock Outputs
The PCIF clock outputs are intended to be used, if required, for systems IOAPIC clock functionality. ANY 2 of the
PCI_F clock outputs can be used as IOAPIC 33Mhz clock outputs. They are 3.3V outputs will be divided down via a
simple resistive voltage divider to meet specific system IOAPIC clock voltage requirements. In the event these clocks
are not required, then these clocks can be used as general PCI clocks or disabled via the assertion of the PCI_STP#
pin.
3V66_1/VCH Clock Output
The 3V66_1/VCH pin has a dual functionality, which is selectable via SMBus.
Configured as DRCG (66M), SMBus Byte0, Bit 5 = ‘0’
The default condition for this pin is to power up in a 66M operation. In 66M operation this output is SSCG capable and
when spreading is turned on, this clock will be modulated.
Configured as VCH (48M), SMBus Byte0, Bit 5 = ‘1’
In this mode, the output is configured as a 48Mhz non-spread spectrum output. This output is phase aligned with the
other 48M outputs (USB and DOT), to within 1ns pin to pin skew. The switching of 3V66_1/VCH into VCH mode
occurs at system power on. When the SMBus Bit 5 of Byte 0 is programmed from a ‘0’ to a ‘1’, the 3V66_1/VCH
output may glitch while transitioning to 48M output mode.
CPU_STP# Clarification
The CPU_STP# signal is an active low input used for synchronous stopping and starting the CPU output clocks while
the rest of the clock generator continues to function.
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