参数资料
型号: CA3290A
厂商: Intersil Corporation
英文描述: BiMOS Dual Voltage Comparators with MOSFET Input, Bipolar Output
中文描述: BiMOS双电压比较器与MOSFET的输入,双极性输出
文件页数: 4/8页
文件大小: 347K
代理商: CA3290A
4
Circuit Description
The Basic Comparator
Figure 4 shows the basic circuit diagram for one of the two
comparators in the CA3290. It is generically similar to the
industry type “139” comparators, with PMOS transistors
replacing PNP transistors as input stage elements. Transistors
Q
1
through Q
4
comprise the differential input stage, with Q
5
and Q
6
serving as a mirror connected active load and
differential-to-single-ended converter. The differential input at
Q
1
and Q
4
is amplified so as to toggle Q
6
in accordance with
the input signal polarity. For example, if +V
IN
is greater than
-V
IN
, Q
1
, Q
2
, and current mirror transistors Q
5
and Q
6
will be
turned off; Transistors Q
3
, Q
4
, and Q
7
will be turned on,
causing Q
8
to be turned off. The output is pulled positive
when a load resistor is connected between the output and V+.
In essence, Q
1
and Q
4
function as source followers to drive
Q
2
and Q
3
, respectively, with zener diodes D
1
through D
4
providing gate oxide protection against input voltage
transients (e.g., static electricity). The current flow in Q
1
and
Q
4
is established at approximately 50
μ
A by constant current
sources I
1
and I
3
, respectively. Since Q
1
and Q
4
are
operated with a constant current load, their gate-to-source
voltage drops will be effectively constant as long as the input
voltages are within the common-mode range.
As a result, the input offset voltage (V
GS(Q1)
+ V
BE(Q2)
-
V
BE(Q3)
- V
GS(Q4)
) will not be degraded when a large
differential DC voltage is applied to the device for extended
periods of time at high temperatures.
Additional voltage gain following the first stage is provided by
transistors Q
7
and Q
8
. The collector of Q
8
is open, offering
the user a wide variety of options in applications. An
additional discrete transistor can be added if it becomes
necessary to boost the output sink current capability.
The detailed schematic diagram for one comparator and the
common current source biasing is shown on the front page.
PMOS transistors Q
9
through Q
12
are the current source
elements identified in Figure 4 as I
1
through I
4
, respectively.
FIGURE 2. NON-INVERTING COMPARATOR RESPONSE TIME TEST CIRCUIT AND WAVEFORMS
FIGURE 3. INVERTING COMPARATOR RESPONSE TIME TEST CIRCUIT AND WAVEFORMS
Test Circuits and Waveforms
INPUT
OVERDRIVE
GND
100mV
OVERDRIVE
20mV
OVERDRIVE
5mV
OVERDRIVE
INPUT
OVERDRIVE
GND
100mV
OVERDRIVE
20mV
OVERDRIVE
5mV
OVERDRIVE
+15V
1K
1K
INPUT
5.1K
OUTPUT
+
-
INPUT
OVERDRIVE
GND
100mV
OVERDRIVE
20mV
OVERDRIVE
5mV
OVERDRIVE
INPUT
OVERDRIVE
GND
100mV
OVERDRIVE
20mV
OVERDRIVE
5mV
OVERDRIVE
+15V
1K
1K
INPUT
5.1K
OUTPUT
+
-
CA3290, CA3290A
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