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参数资料
| 型号： | CA3306M |
| 厂商： | INTERSIL CORP |
| 元件分类： | ADC |
| 英文描述： | 6-Bit, 15 MSPS, Flash A/D Converters |
| 中文描述： | 1-CH 6-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO20 |
| 封装： | PLASTIC, SOIC-20 |
| 文件页数： | 11/16页 |
| 文件大小： | 111K |
| 代理商： | CA3306M |
4-18
The CA3306 outputs a short (less than 10ns) current spike
of up to several mA amplitude (See Typical Performance
Curves) at the beginning of the sample phase. (To a lesser
extent, a spike also appears at the beginning of auto bal-
ance.) The driving source must recover from the spike by the
end of the same phase, or a loss of accuracy will result.
A locally terminated 50
or 75
source is generally suffi-
cient to drive the CA3306. If gain is required, a high speed,
fast settling operational amplifier, such as the HA-5033,
HA-2542, or HA5020 is recommended.
Digital Input And Output Interfacing
The two chip-enable and the phase-control inputs are stan-
dard CMOS units. They should be driven from less than 0.3
x V
DD
to at least 0.7 x V
DD
. This can be done from 74HC
series CMOS (QMOS), TTL with pull-up resistors, or, if V
DD
is greater than the logic supply, open collector or open drain
drivers plus pull-ups. (See Figure 20.)
The clock input is more critical to timing variations, such as
φ
1 becoming too short, for instance. Pull-up resistors should
generally be avoided in favor of active drivers. The clock
input may be capacitively coupled, as it has an internal 50k
feedback resistor on the first buffer stage, and will seek its
own trip point. A clock source of at least 1V
P-P
is adequate,
but extremely non-symmetrical waveforms should be
avoided.
The output drivers have full rail-to-rail capability. If driving
CMOS systems with V
DD
below the V
DD
of the CA3306, a
CD74HC4050 or CD74HC4049 should be used to step down
the voltage. If driving LSTTL systems, no step-down should
be necessary, as most LSTTLs will take input swings up to
10V to 15V.
Although the output drivers are capable of handling typical
data bus loading, the capacitor charging currents will pro-
duce local ground disturbances. For this reason, an external
bus driver is recommended.
Increased Accuracy
In most cases the accuracy of the CA3306 should be
sufficient without any adjustments. In applications where
accuracy is of utmost importance, three adjustments can be
made to obtain better accuracy; i.e., offset trim, gain trim,
and midpoint trim.
Offset Trim
In general offset correction can be done in the preamp
circuitry by introducing a DC shift to V
lN
or by the offset trim
of the operational amplifier. When this is not possible the
V
REF
- input can be adjusted to produce an offset trim. The
theoretical input voltage to produce the first transition is
1
/
2
LSB. The equation is as follows:
V
IN
(0 to 1 transition) =
1
/
2
LSB =
1
/
2
(V
REF
/64)
= V
REF
/128.
If V
lN
for the first transition is less than the theoretical, then a
single-turn 50
pot connected between V
REF
- and ground will
accomplish the adjustment. Set V
lN
to
1
/
2
LSB and trim the pot
until the 0 to 1 transition occurs.
If V
IN
for the first transition is greater than the theoretical,
then the 50
pot should be connected between V
REF
and a
negative voltage of about 2 LSBs. The trim procedure is as
stated previously.
Gain Trim
In general the gain trim can also be done in the preamp
circuitry by introducing a gain adjustment for the operational
amplifier. When this is not possible, then a gain adjustment
circuit should be made to adjust the reference voltage. To
perform this trim, V
lN
should be set to the 63 to overflow
transition. That voltage is
1
/
2
LSB less than V
REF
+ and is
calculated as follows:
V
lN
(63 to 64 transition) = V
REF
- V
REF
/128
= V
REF
(127/128).
To perform the gain trim, first do the offset trim and then
apply the required V
lN
for the 63 to overtlow transition. Now
adjust V
REF
+ until that transition occurs on the outputs.
Midpoint Trim
The reference center (RC) is available to the user as the
midpoint of the resistor ladder. To trim the midpoint, the
offset and gain trims should be done first. The theoretical
transition from count 31 to 32 occurs at 31
1
/
2
LSBs. That
voltage is as follows:
V
lN
(31 to 32 transition) = 31.5 (V
REF
/64)
= V
REF
(63/128).
An adjustable voltage follower can be connected to the RC
pin or a 2K pot can be connected between V
REF
+ and
V
REF
- with the wiper connected to RC. Set V
lN
to the 31 to
32 transition voltage, then adjust the voltage follower or the
pot until the transition occurs on the output bits.
The Reference Center point can also be used to create
unique transfer functions. The user must remember, however,
that there is approximately 120
in series with the RC pin.
Applications
7-Bit Resolution
To obtain 7-bit resolution, two CA3306s can be wired
together. Necessary ingredients include an open-ended lad-
der network, an overtlow indicator, three-state outputs, and
chip-enabler controls - all of which are available on the
CA3306.
The first step for connecting a 7-bit circuit is to totem-pole
the ladder networks, as illustrated in Figure 17. Since the
absolute resistance value of each ladder may vary, external
trim of the mid-reference voltage may be required.
The overflow output of the lower device now becomes the
seventh bit. When it goes high, all counts must come from
the upper device. When it goes low, all counts must come
from the lower device. This is done simply by connecting the
lower overflow signal to the CE1 control of the lower A/D
converter and the CE2 control of the upper A/D converter.
The three-state outputs of the two devices (bits 1 through 6)
are now connected in parallel to complete the circuitry.
CA3306, CA3306A, CA3306C
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相关代理商/技术参数 |
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|---|---|
| CA3306M96 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CA3308AD | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Converter IC |
| CA3308D | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Converter IC |
| CA33-1 | 制造商:MA-COM 制造商全称:M/A-COM Technology Solutions, Inc. 功能描述:Cascadable Amplifier 2 to 2400 MHz |
| CA3310 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:CMOS, 10-Bit, A/D Converters with Internal Track and Hold |
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