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参数资料
| 型号： | CA3310A |
| 厂商： | Intersil Corporation |
| 元件分类： | 串行ADC |
| 英文描述： | CMOS, 10-Bit, A/D Converters with Internal Track and Hold |
| 中文描述： | 的CMOS，10位，在A / D内部跟踪和保持转换器 |
| 文件页数： | 14/15页 |
| 文件大小： | 120K |
| 代理商： | CA3310A |
6-19
Single +5V Supply
If only a single +5V supply is available, an ICL7660 can be
used to provide approximately +8V and -4V to the opera-
tional amplifier. Figure 20 shows this approach. Note that the
converter and associated capacitors should be grounded to
the digital supply. The 1k
in series with each supply at the
operational amplifier isolates digital and analog grounds.
Digital Sample and Hold
With a minimum of external logic, the CA3310 can be made
to wait at the verge of ending a sample. A start pulse will then,
after the internal aperture delay, capture the input and finish
the conversion cycle. Figure 21 illustrates this application.
The CA3310 is connected as if to free run. The Data Ready
signal is shifted through a CD74HC175, and at the low-going
clock edge just before the sample would end, is used to hold
the clock low.
The same signal, active high, is available to indicate the
CA3310 is ready to convert. A low pulse to reset the
CD74HC175 will now release the clock, and the sample will
end as it goes positive. Ten cycles later, the conversion will
be complete, and DRDY will go active.
Operating and Handling Considerations
HANDLING
All inputs and outputs of Intersil CMOS devices have a
network for electrostatic protection during handling. Recom-
mended handling practices for CMOS devices are described
in lCAN-6526, “Guide to Better Handling and Operation of
CMOS Integrated Circuits”.
OPERATING
Operating Voltage
During operation near the maximum supply voltage limit,
care should be taken to avoid or suppress power supply
turn-on and turn-off transients, power supply ripple, or
ground noise; any of these conditions must not cause
V
DD
- V
SS
to exceed the absolute maximum rating.
Input Signals
To prevent damage to the input protection circuit, input
signals should never be greater than V
DD
+0.3V nor less
than V
SS
-0.3V. Input currents must not exceed 20mA even
when the power supply is off.
Unused Inputs
A connection must be provided at every input terminal. All
unused Input terminals must be connected to either V
DD
or
V
SS
, whichever is appropriate.
Output Short Circuits
Shorting of outputs to V
DD
or V
SS
may damage CMOS
devices by exceeding the maximum device dissipation.
+5V
+
8
D
2
IN914
+8V
-4V
4
5
3
ICL7660S
ALL CAPACITORS - 10
μ
F, 10V
D = DIGITAL GROUND
D
D
D
+
+
+
+
10
CA3310/A
V
DD
V
AA
+
V
REF
+
V
IN
V
REF
-
V
AA
-
V
SS
DRST
STRT
D0 - D9
OEL
OEM
DRDY
R
EXT
CLK
A
D
INPUT BUFFED
AS REQUIRED
ANALOG
INPUT
FULL SCALE
REFERENCE
+5V
DATA TO SYSTEM
OUTPUT ENABLES
DATA READY
A
A
D
+5V
D
IN914
1/16
READY TO
CONVERT
+5V
D
START
CONVERT
NC
D0
Q0
D1
Q1
Q2
Q2
D3
Q0
Q1
Q3
Q3
MR
CD74HCO4E
D2
D
CD74HC175E
CP
V
DD
GND
KEEP CAPACITANCE AT R
EXT
/CLK NODE
AS LOW AS POSSIBLE
D = DIGITAL GROUND
A = ANALOG GROUND
FIGURE 20. DIGITAL TRACK-AND-HOLD BLOCK DIAGRAM
CA3310, CA3310A
相关PDF资料 |
PDF描述 |
|---|---|
| CA3310AD | CMOS, 10-Bit, A/D Converters with Internal Track and Hold |
| CA3310AE | CMOS, 10-Bit, A/D Converters with Internal Track and Hold |
| CA3310AM | CMOS, 10-Bit, A/D Converters with Internal Track and Hold |
| CA3310D | CMOS, 10-Bit, A/D Converters with Internal Track and Hold |
| CA3310E | CMOS, 10-Bit, A/D Converters with Internal Track and Hold |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CA3310AD | 制造商:Rochester Electronics LLC 功能描述: |
| CA3310AE | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| CA3310AE97 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CA3310AM | 制造商:Rochester Electronics LLC 功能描述: |
| CA3310D | 制造商:Harris Corporation 功能描述: |
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