- 您现在的位置：买卖IC网 > PDF目录379729 > CA3310AD (HARRIS SEMICONDUCTOR) CMOS, 10-Bit, A/D Converters with Internal Track and Hold PDF资料下载
参数资料
| 型号： | CA3310AD |
| 厂商： | HARRIS SEMICONDUCTOR |
| 元件分类： | ADC |
| 英文描述： | CMOS, 10-Bit, A/D Converters with Internal Track and Hold |
| 中文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP24 |
| 文件页数： | 5/15页 |
| 文件大小： | 120K |
| 代理商： | CA3310AD |
6-10
DIGITAL OUTPUTS
D0 - D9, DRDY
High-Level Output Voltage
I
SOURCE
= -4mA
I
SINK
= 6mA
Except DRDY
4.6
-
-
V
Low-Level Output Voltage
-
-
0.4
V
Three-State Leakage
-
-
±
1
μ
A
Output Capacitance
Except DRDY (Note 2)
-
-
20
pF
CLK OUTPUT
High-Level Output Voltage
I
SOURCE
= 100
μ
A (Note 2)
I
SlNK
= 100
μ
A (Note 2)
4
-
-
V
Low-Level Output Voltage
-
-
1
V
TIMING
Clock Frequency
Internal, CLK and R
EXT
Open
Internal, CLK Shorted to R
EXT
External, Applied to CLK (Note 2) (Max)
200
300
400
kHz
600
800
1000
kHz
-
4
2
MHz
(Min)
100
10
-
kHz
Clock Pulse Width, t
LOW
, t
HIGH
External, Applied to CLK:
See Figure 1 (Note 2)
100
-
-
ns
Conversion Time
Internal, CLK Shorted to R
EXT
See Figure 1
13
-
-
μ
s
Aperture Delay, t
D
APR
Clock to Data Ready Delay, t
D1
DRDY
Clock to Data Ready Delay, t
D2
DRDY
Clock to Data Delay, t
D
Data
Start Removal Time, t
R
STRT
Start Setup Time, t
SU
STRT
Start Pulse Width, t
W
STRT
Start to Data Ready Delay, t
D3
DRDY
Clock Delay from Start, t
D
CLK
Ready Reset Removal Time, t
R
DRST
Ready Reset Pulse Width, t
W
DRST
Ready Reset to Data Ready Delay,
t
D4
DRDY
Output Enable Delay, t
EN
Output Disable Delay, t
DIS
SUPPLIES
-
100
-
ns
See Figure 1
-
150
-
ns
See Figure 1
-
250
-
ns
See Figure 1
-
200
-
ns
See Figures 3 and 4 (Note 1)
-
-120
-
ns
See Figure 4
-
160
-
ns
See Figures 3 and 4
-
10
-
ns
See Figures 3 and 4
-
170
-
ns
See Figure 3
-
200
-
ns
See Figure 50 (Note 1)
-
-80
-
ns
See Figure 5
-
10
-
ns
See Figure 5
-
35
-
ns
See Figure 2
-
40
-
ns
See Figure 2
-
50
-
ns
Supply Operating Range, V
DD
or V
AA
Supply Current, I
DD
+ I
AA
Supply Standby Current
(Note 2)
3
-
6
V
See Figures 14, 15
-
3
8
mA
Clock Stopped During Cycle 1
-
3.5
-
mA
Analog Supply Rejection
At 120Hz, See Figure 13
-
25
-
mV/V
Reference Input Current
See Figure 10
-
160
-
μ
A
TEMPERATURE DEPENDENCY
Offset Drift
At 0 to 1 Code Transition
-
-4
-
μ
V/
o
C
μ
V/
o
C
%/
o
C
Gain Drift
At 1022 to 1023 Code Transition
-
-6
-
Internal Clock Speed
See Figure 7
-
-0.5
-
NOTES:
1. A (-) removal time means the signal can be removed after the reference signal.
2. Parameter not tested, but guaranteed by design or characterization.
Electrical Specifications
T
A
= 25
o
C, V
DD
= V
AA
+ = 5V, V
REF
+ = 4.608V, V
SS
= V
AA
- = V
REF
- = GND, CLK = External 1MHz,
Unless Otherwise Specified
(Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
CA3310, CA3310A
相关PDF资料 |
PDF描述 |
|---|---|
| CA3310AE | CMOS, 10-Bit, A/D Converters with Internal Track and Hold |
| CA3310AM | CMOS, 10-Bit, A/D Converters with Internal Track and Hold |
| CA3310D | CMOS, 10-Bit, A/D Converters with Internal Track and Hold |
| CA3310E | CMOS, 10-Bit, A/D Converters with Internal Track and Hold |
| CA3310M | CMOS, 10-Bit, A/D Converters with Internal Track and Hold |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CA3310AE | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| CA3310AE97 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CA3310AM | 制造商:Rochester Electronics LLC 功能描述: |
| CA3310D | 制造商:Harris Corporation 功能描述: |
| CA3310E | 制造商:Rochester Electronics LLC 功能描述:24PDIP,-40+85,10-BITCMOSA/D " - Bulk |
发布紧急采购，3分钟左右您将得到回复。