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参数资料
| 型号： | CA3310AM |
| 厂商： | INTERSIL CORP |
| 元件分类： | ADC |
| 英文描述： | CMOS, 10-Bit, A/D Converters with Internal Track and Hold |
| 中文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| 封装： | PLASTIC, MS-013AD, SOIC-24 |
| 文件页数： | 4/15页 |
| 文件大小： | 120K |
| 代理商： | CA3310AM |
6-9
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage V
DD
. . . . . . . . . . . . . . .V
SS
-0.5V to V
SS
+7V
Analog Supply Voltage (V
AA
+) . . . . . . . . . . . . . . . . . . . . .V
DD
±
0.5V
Any Other Terminal. . . . . . . . . . . . . . . . .V
SS
-0.5V to V
DD
+ 0.5V
DC Input Current or Output (Protection Diode)
Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
20mA
DC Output Drain Current, per Output. . . . . . . . . . . . . . . . . .
±
35mA
Total DC Supply or Ground Current . . . . . . . . . . . . . . . . . . .
±
70mA
Operating Conditions
Temperature Range (T
A
)
Package Type D . . . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Package Type E, M. . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Thermal Resistance (Typical, Note 1)
PDIP Package . . . . . . . . . . . . . . . . . . . . .
SBDIP Package. . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Hermetic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
o
C
Maximum Storage Temperature (T
STG
) . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
θ
JA
(
o
C/W)
θ
JC
(
o
C/W)
N/A
22
N/A
75
70
75
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
T
A
= 25
o
C, V
DD
= V
AA
+ = 5V, V
REF
+ = 4.608V, V
SS
= V
AA
- = V
REF
- = GND, CLK = External 1MHz,
Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ACCURACY
(See Text For Definitions)
Resolution
10
-
-
Bits
Differential Linearity Error
CA3310
-
±
0.5
±
0.75
LSB
CA3310A
-
±
0.25
±
0.5
LSB
Integral Linearity Error
CA3310
-
±
0.5
±
0.75
LSB
CA3310A
-
±
0.25
±
0.5
LSB
Gain Error
CA3310
-
±
0.25
±
0.5
LSB
CA3310A
-
-
±
0.25
LSB
Offset Error
CA3310
-
±
0.25
±
0.5
LSB
CA3310A
-
-
±
0.25
LSB
ANALOG OUTPUT
Input Resistance
In Series with Input Sample
Capacitors
-
330
-
Input Capacitance
During Sample State
-
300
-
pF
Input Capacitance
During Hold State
-
20
-
pF
Input Current
At V
IN
= V
REF
+ = 5V
At V
IN
= V
REF
- = 0V
STRT = V+, CLK = V+
At V
IN
= V
REF
+ = 5V
At V
IN
= V
REF
- = 0V
(Note 2)
-
-
+300
μ
A
-
-
-100
μ
A
Static Input Current
-
-
1
μ
A
-
-
-1
μ
A
Input + Full-Scale Range
V
REF
- +1
V
SS
-0.3
-
-
V
DD
+0.3
V
REF
+ -1
-
V
Input - Full-Scale Range
(Note 2)
-
V
Input Bandwidth
From Input RC Time Constant
1.5
MHz
DIGITAL INPUTS
DRST, OEL, OEM, STRT, CLK
High-Level Input Voltage
Over V
DD
= 3V to 6V (Note 2)
70
-
-
% of
V
DD
% of
V
DD
μ
A
Low-Level Input Voltage
Over V
DD
= 3V to 6V (Note 2)
-
-
30
Input Leakage Current
Except CLK
-
-
±
1
Input Capacitance
(Note 2)
-
-
10
pF
Input Current
CLK Only (Note 2)
-
-
±
400
μ
A
CA3310, CA3310A
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