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参数资料
| 型号： | CA3310E |
| 厂商： | INTERSIL CORP |
| 元件分类： | ADC |
| 英文描述： | CMOS, 10-Bit, A/D Converters with Internal Track and Hold |
| 中文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP24 |
| 封装： | PLASTIC, MS-011AA, DIP-24 |
| 文件页数： | 11/15页 |
| 文件大小： | 120K |
| 代理商： | CA3310E |
6-16
will shut off after entering period 2. The input will continue to
track the DRDY output will remain high during this time.
A low signal applied to STRT (at least t
W
STRT wide) can
now initiate a new conversion. The STRT signal (after a
delay of t
D3
DRDY) will cause the DRDY flag to drop, and
(after a delay of t
D
CLK) cause the clock to restart.
Depending on how long the clock was shut off, the low
portion of clock period 2 may be longer than during the
remaining cycles.
The input will continue to track until the end of period 3, the
same as when free-running.
Figure 4 illustrates the same operation as above, but with an
external clock. If STRT is removed (at least t
R
STRT) before
clock period 1, and not reapplied during that period, the
clock will continue to cycle in period 2. A low signal applied
to STRT will drop the DRDY flag as before, and with the first
positive-going clock edge that meets the t
SU
STRT set-up
time, the converter will continue with clock period 3.
The DRDY flag output, as described previously, goes active
at the start of period 1, and drops at the start of period 2 or
upon a new STRT command, whichever is later. It may also
be controlled with the DRST (Data Ready Reset) input.
Figure 5 depicts this operation.
DRST must be removed (at least t
R
DRST) before the start
of period 1 to allow DRDY to go high. A low level on DRST
(at least t
W
DRST wide) will (after a delay of t
D4
DRDY) drop
DRDY.
Analog Input
The analog input pin is a predominantly capacitive load that
changes between the track and hold periods of a conversion
cycle. During hold, clock period 4 through 13, the input
loading is leakage and stray capacitance, typically less than
0.1
μ
A and 20pF.
At the start of input tracking, clock period 1, some charge is
dumped back to the input pin. The input source must have low
enough impedance to dissipate the charge by the end of the
tracking period. The amount of charge is dependent on supply
and input voltages. Figure 8 shows typical peak input currents
for various supply and input voltages, while Figure 9 shows
typical average input currents. The average current is also pro-
portional to clock frequency, and should be scaled accordingly.
During tracking, the input appears as approximately a 300pF
capacitor in series with 330
,
for a 100ns time constant. A
full-scale input swing would settle to
1
/
2
LSB (
1
/
2048
) in 7RC
time constants. Doing continuous conversions with a 1MHz
clock provides 3
μ
s of tracking time, so up to 1k
of external
source impedance (400ns time constant) would allow proper
settling of a step input.
If the clock was slower, or the converter was not restarted
immediately (causing a longer sample lime), a higher source
impedance could be used.
The CA3310s low-input time constant also allows good
tracking of dynamic input waveforms. The sampling rate with
a 1MHz clock is approximately 80kHz. A Nyquist rate
(f
SAMPLE
/2) input sine wave of 40kHz would have negligible
attenuation and a phase lag of only 1.5 degrees.
Accuracy Specifications
The CA3310 accepts an analog input between the values of
V
REF
- and V
REF
+, and quantizes it into one of 2
10
or 1024
output codes. Each code should exist as the input is varied
through a range of
1
/
1024
X (V
REF
+ - V
REF
-), referred to as
1 LSB of input voltage. A differential Iinearity error, illustrated
in Figure 17, occurs if an output code occurs over other than
the ideal (1 LSB) input range. Note that as long as the error
does not reach -1 LSB, the converter will not miss any codes.
The CA3310 output should change from a code of 000
16
to
001
16
at an input voltage of (V
REF
- +1 LSB). It should also
change from a code of 3FE
16
to 3FF
16
at an input of
(V
REF
+ -1 LSB). Any differences between the actual and
expected input voltages that cause these transitions are the
offset and gain errors, respectively. Figure 18 illustrates
these errors.
As the input voltage is increased linearly from the point that
causes the 000
16
to 001
16
transition to the point that causes
the 3FE
16
to 3FF
16
transition, the output code should also
increase linearly. Any deviation from this input-to-output cor-
respondence is integral linearity error, illustrated in Figure 19.
Note that the integral linearity is referenced to a straight line
drawn through the actual end points, not the ideal end
points. For absolute accuracy to be equal to the integral lin-
earity, the gain and offset would have to be adjusted to ideal.
Offset and Gain Adjustments
The V
REF
+ and V
REF
- pins, references for the two ends of
the analog input range, are the only means of doing offset or
gain adjustments. In a typical system, the V
REF
- might be
returned to a clean ground, and offset adjustment done on
an input amplifier. V
REF
+ would then be adjusted for gain.
V
REF
- could be raised from ground to adjust offset or to accom-
modate an input source that can’t drive down to ground. There
are current pulses that occur, however, during the successive
approximation part of a conversion cycle, as the charge-balanc-
ing capacitors are switched between V
REF
- and V
REF
+. For
that reason, V
REF
- and V
REF
+ should be well bypassed.
Figure 10 shows peak and average V
REF
+ current.
UNIFORM
TRANSFER
CURVE
A
B
C
ACTUAL
TRANSFER
CURVE
OUTPUT
CODE
A = IDEAL 1 LSB STEP
B-A = + DIFFERENTIAL LINEARITY ERROR
A-C = - DIFFERENTIAL LINEARITY ERROR
INPUT VOLTAGE
FIGURE 17. DIFFERENTIAL LINEARITY ERROR
CA3310, CA3310A
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