4-20
Reducing Power
Most power is consumed while in the auto-balance state.
When operating at lower than 15MHz clock speed, power
can be reduced by stretching the sample (
φ
2) time. The con-
straints are a minimum balance time (
φ
1) of 33ns, and a
maximum sample time of 500ns. Longer sample times cause
droop in the auto-balance capacitors. Power can also be
reduced in the reference string by switching the reference on
only during auto-balance.
Clock Input
The Clock and Phase inputs feed buffers referenced to V
AA
+
and V
AA
-. Phase should be tied to one of these two poten-
tials, while the clock (if DC coupled) should be driven at least
from 0.2 to 0.7 x (V
AA
+ - V
AA
-). The clock may also be AC
coupled with at least a 1V
P-P
swing. This allows TTL drive
levels or 5V QMOS levels when V
AA
+ is greater than 5V.
TABLE 1. OUTPUT CODE TABLE
CODE
DESCRIPTION
(NOTE 1)
INPUT VOLTAGE
BINARY OUTPUT CODE
DECIMAL
COUNT
V
REF
6.40V (V)
V
REF
5.12V (V)
OF
MSB
B8
B7
B6
B5
B4
B3
B2
LSB
B1
Zero
0.00
0.00
0
0
0
0
0
0
0
0
0
0
1 LSB
0.025
0.02
0
0
0
0
0
0
0
0
1
1
2 LSB
0.05
0.04
0
0
0
0
0
0
0
1
0
2
1
/
4
Full Scale
1.60
1.28
0
0
1
0
0
0
0
0
0
64
1
/
2
Full Scale - 1 LSB
3.175
2.54
0
0
1
1
1
1
1
1
1
127
1
/
2
Full Scale
3.20
2.56
0
1
0
0
0
0
0
0
0
128
1
/
2
Full Scale + 1 LSB
3.225
2.58
0
1
0
0
0
0
0
0
1
129
3
/
4
Full Scale
4.80
3.84
0
1
1
0
0
0
0
0
0
192
Full Scale - 1 LSB
6.35
5.08
0
1
1
1
1
1
1
1
0
254
Full Scale
6.375
5.10
0
1
1
1
1
1
1
1
1
255
Over Flow
6.40
5.12
1
1
1
1
1
1
1
1
1
511
NOTE: 1. The voltages listed above are the ideal centers of each output code shown as a function of its associated reference voltage.
CA3318
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