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参数资料
| 型号： | CA3338AD |
| 厂商： | INTERSIL CORP |
| 元件分类： | DAC |
| 英文描述： | CMOS Video Speed, 8-Bit, 50 MSPS, R2R D/A Converters |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 0.02 us SETTLING TIME, 8-BIT DAC, CDIP16 |
| 封装： | SIDE BRAZED, DIP-16 |
| 文件页数： | 4/7页 |
| 文件大小： | 59K |
| 代理商： | CA3338AD |
10-14
Digital Signal Path
The digital inputs (LE, COMP, and D0 - D7) are of TTL
compatible HCT High Speed CMOS design: the loading is
essentially capacitive and the logic threshold is typically
1.5V.
The 8 data bits, D0 (weighted 2
0
) through D7 (weighted 2
7
),
are applied to Exclusive OR gates (see Functional Diagram).
The COMP (data complement) control provides the second
input to the gates: if COMP is high, the data bits will be
inverted as they pass through.
The input data and the LE (latch enable) signals are next
applied to a level shifter. The inputs, operating between the
levels of V
DD
and V
SS
, are shifted to operate between V
DD
and V
EE
. V
EE
optionally at ground or at a negative voltage,
will be discussed under bipolar operation. All further logic
elements except the output drivers operate from the V
DD
and V
EE
supplies.
The upper 3 bits of data, D5 through D7, are input to a 3-to-7
line bar graph encoder. The encoder outputs and D0 through
D4 are applied to a feedthrough latch, which is controlled by
LE (latch enable).
REFERENCE VOLTAGE
V
REF
+ Range
V
REF
- Range
V
REF
+ Input Current
SUPPLY VOLTAGE
(+) Full Scale, Note 1
V
REF
- + 3
V
EE
-
-
V
DD
V
(-) Full Scale, Note 1
-
V
REF
+ - 3
50
V
V
REF
+ = 6V, V
DD
= 6V
40
mA
Static I
DD
or I
EE
LE = Low, D0 - D7 = High
-
100
220
μ
A
LE = Low, D0 - D7 = Low
-
-
100
μ
A
Dynamic I
DD
or I
EE
Dynamic I
DD
or I
EE
V
DD
Rejection
V
EE
Rejection
DIGITAL INPUTS
V
OUT
= 10MHz, 0V to 5V Square Wave
V
OUT
= 10MHz,
±
2.5V Square Wave
50kHz Sine Wave Applied
-
20
-
mA
-
25
-
mA
-
3
-
mV/V
50kHz Sine Wave Applied
-
1
-
mV/V
D0 - D7, LE, COMP
High Level Input Voltage
Note 1
2
-
-
V
Low Level Input Voltage
Note 1
-
-
0.8
V
Leakage Current
-
±
1
±
5
μ
A
Capacitance
-
5
-
pF
TEMPERATURE COEFFICIENTS
Output Impedance
-
200
-
ppm/
o
C
NOTE:
1. Parameter not tested. but guaranteed by design or characterization.
Electrical Specifications
T
A
= 25
o
C, V
DD
= 5V, V
REF
+ = 4.608V, V
SS
= V
EE
= V
REF
- = GND, LE Clocked at 20MHz, R
L
≥
1 M
,
Unless Otherwise Specified
(Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Pin Descriptions
PIN
NAME
DESCRIPTION
1
D7
Most Significant Bit
2
D6
Input
3
D5
Data
4
D4
Bits
5
D3
(High = True)
6
D2
7
D1
8
V
SS
Digital Ground
9
D
0
Least Significant Bit. Input Data Bit
10
V
EE
Analog Ground
11
V
REF
-
Reference Voltage Negative Input
12
V
OUT
Analog Output
13
V
REF
+
Reference Voltage Positive Input
14
COMP
Data Complement Control input. Active High
15
LE
Latch Enable Input. Active Low
16
V
DD
Digital Power Supply, +5V
CA3338, CA3338A
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