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参数资料
| 型号： | CA3338AE |
| 厂商： | HARRIS SEMICONDUCTOR |
| 元件分类： | DAC |
| 英文描述： | CMOS Video Speed, 8-Bit, 50 MSPS, R2R D/A Converters |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 0.02 us SETTLING TIME, 8-BIT DAC, PDIP16 |
| 文件页数： | 5/7页 |
| 文件大小： | 59K |
| 代理商： | CA3338AE |
10-15
Latch Operation
Data is fed from input to output while LE is low: LE should be
tied low for non-clocked operation.
Non-clocked operation or changing data while LE is low is
not recommended for applications requiring low output
“glitch” energy: there is no guarantee of the simultaneous
changing of input data or the equal propagation delay of all
bits through the converter. Several parameters are given if
the converter is to be used in either of these modes: t
D2
gives the delay from the input changing to the output chang-
ing (10%), while t
SU2
and t
H
give the set up and hold times
(referred to LE rising edge) needed to latch data. See
Figures 1 and 2.
Clocked operation is needed for low “glitch” energy use.
Data must meet the given t
SU1
set up time to the LE falling
edge, and the t
H
hold time from the LE rising edge. The
delay to the output changing, t
D1
, is now referred to the LE
falling edge.
There is no need for a square wave LE clock; LE must only
meet the minimum t
W
pulse width for successful latch opera-
tion. Generally, output timing (desired accuracy of settling)
sets the upper limit of usable clock frequency.
Output Structure
The latches feed data to a row of high current CMOS drivers,
which in turn feed a modified R2R ladder network.
The “N” channel (pull down) transistor of each driver plus the
bottom “2R” resistor are returned to V
REF
- this is the (-) full-
scale reference. The “P” channel (pull up) transistor of each
driver is returned to V
REF
+, the (+) full-scale reference.
In unipolar operation, V
REF
- would typically be returned to
analog ground, but may be raised above ground (see specifi-
cations). There is substantial code dependent current that
flows from V
REF
+ to V
REF
- (see V
REF
+ input current in
specifications), so V
REF
- should have a low impedance path
to ground.
In bipolar operation, V
REF
- would be returned to a negative
voltage (the maximum voltage rating to V
DD
must be
observed). V
EE
, which supplies the gate potential for the
output drivers, must be returned to a point at least as nega-
tive as V
REF
-. Note that the maximum clocking speed
decreases when the bipolar mode is used.
Static Characteristics
The ideal 8-bit D/A would have an output equal to V
REF
- with
an input code of 00
HEX
(zero scale output), and an output
equal to 255/256 of V
REF
+ (referred to V
REF
-) with an input
code of FFHEX(full scale output). The difference between the
ideal and actual values of these two parameters are the OFF-
SET and GAIN errors, respectively; see Figure 3.
If the code into an 8-bit D/A is changed by 1 count, the output
should change by 1/255 (full scale output - zero scale output). A
deviation from this step size is a differential linearity error, see
Figure 4. Note that the error is expressed in fractions of the
ideal step size (usually called an LSB). Also note that if the (-)
differential linearity error is less (in absolute numbers) than 1
LSB, the device is monotonic. (The output will always increase
for increasing code or decrease for decreasing code).
If the code into an 8-bit D/A is at any value, say “N”, the output
voltage should be N/255 of the full scale output (referred to the
zero scale output). Any deviation from that output is an integral
linearity error, usually expressed in LSBs. See Figure 4.
Note that OFFSET and GAIN errors do not affect integral
linearity, as the linearity is referenced to actual zero and full
scale outputs, not ideal. Absolute accuracy would have to
also take these errors into account.
INPUT DATA
LATCH
ENABLE
t
SU1
t
SU2
t
W
t
H
LATCHED
LATCHED
DATA
FEEDTHROUGH
FIGURE 1. DATA TO LATCH ENABLE TIMING
t
D1
t
D2
t
r
t
S
1
/
2
LSB
1
/
2
LSB
90%
10%
INPUT
DATA
LATCH
ENABLE
OUTPUT
VOLTAGE
FIGURE 2. DATA AND LATCH ENABLE TO OUTPUT TIMING
255/256
254/256
253/256
3/256
2/256
1/256
0
00
01
02
03
FD
FE
FF
= IDEAL TRANSFER CURVE
= ACTUAL TRANSFER CURVE
OFFSET
ERROR
(SHOWN +)
O
R
+
R
-
GAIN ERROR
(SHOWN -)
INPUT CODE IN HEXADECIMAL (COMP = LOW)
FIGURE 3. D/A OFFSET AND GAIN ERROR
CA3338, CA3338A
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| CA3338AMZ96 | 功能描述:数模转换器- DAC 16(W INDTEMP VID D/A 8BIT 50MHZ 0 75 LSB RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
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