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参数资料
| 型号： | CA95C09-16CT |
| 元件分类： | 加密电路 |
| 英文描述： | TELECOM, DATA ENCRYPTION CIRCUIT, PQFP44 |
| 封装： | TQFP-44 |
| 文件页数： | 39/42页 |
| 文件大小： | 180K |
| 代理商： | CA95C09-16CT |
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CA95C68/18/09
Tundra Semiconductor Corporation
3-30
Tundra Semiconductor Corporation
–
––29
23
I
Master Port Read or Master Port Data Strobe: (For CA95C09) When the
OPTION pin is HIGH this input functions as
. When the OPTION pin is
LOW this input functions as
. (See appropriate pin description).
MALE –
_
–
30
24
I
Master Port Address Latch Enable or Master Port Address Strobe: (For
CA95C09) When the OPTION pin is HIGH this input functions as MALE and
when OPTION is LOW it functions as
. (See the appropriate pin
description).
–
MR/W
––31
25
I
Master Port Write or Master Port Read/Write: (For CA95C09) When the
OPTION pin is HIGH this input functions as
and when OPTION is
LOW it functions as MR/W. (See the appropriate pin description).
15
16
17
11
O
Master Port Flag: This active LOW ag indicates the need for a data transfer
into or out of the Master Port during normal ciphering operation. The Master
Port will be associated with either the Input or Output Register depending
upon the setting of the Control bits in the Mode Register (See Register
Description).
If data is to be transferred through the Master Port to the Input Register, then
reects the contents of the Input Register. After any Start command
is entered,
will go active (LOW) whenever the Input Register is not
full.
is forced HIGH by any command other than a Start.
Conversely, if the Master Port is associated with the Output Register,
reects the contents of the Output Register (except in single port
conguration; see Functional Description). Whenever the Output Register is
not empty
will be active (LOW). In single port mode of operation, the
Master Port ag reects the contents of the Input Register, while the Slave
Port Flag (
, see below) is associated with the Output Register.
SP7–SP0
36-39
5-2
40-43
6-3
40-43
6-3
34-37
44-41
I/O
Slave Port Bus: This 8 bit bi-directional data bus provides a second
input/output interface to the DCP, allowing overlapped input, ciphering and
output operations. The tri-state Slave Port will be accessed only when the
Mode Register is congured for dual port operation, Slave Port Chip Select
(
) and Slave Port Data Strobe (
) are both LOW and
=0.
Data entered or retrieved through this port is the most signicant byte in/out
rst (SP7 is the most signicant bit).
Table 3-2 : Pin Description Cont'd
Symbol
95C68/18
95C09
TYPE
Name and Function
PDIP
PLCC
TQFP
MRD
MDS
MRD
MDS
MAS
MWR
MFLG
SFLG
SCS
SDS
SFLG
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