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| 型号： | CA95C09-5CT |
| 元件分类： | 加密电路 |
| 英文描述： | TELECOM, DATA ENCRYPTION CIRCUIT, PQFP44 |
| 封装： | TQFP-44 |
| 文件页数： | 14/42页 |
| 文件大小： | 180K |
| 代理商： | CA95C09-5CT |
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Tundra Semiconductor Corporation
CA95C68/18/09
Tundra Semiconductor Corporation
3-45
FUNCTIONAL DESCRIPTION
Multiple Key Registers
The DCP provides the necessary registers to implement a
multiple-key system. In such an arrangement, a single
Master Key, stored in the DCP M Key Register, is used only
to encrypt session keys for transmission to remote DES
equipment, and to decrypt session keys received from such
equipment. The M Key Register may only be loaded with
plain text through the Auxiliary Port, using the Load Clear M
Key command.
In addition to the Master Key Register, the DCP contains two
Session Key Registers; the E Key Register, used to encrypt
clear text, and the D Key Register, used to decrypt cipher
text. All three registers are loaded by writing commands
through the Master Port (Multiplexed Control Mode) into the
Command Register, and then writing the eight bytes of key
data to the port when the Command Pending bit = “1” in the
Status Register (see Command Description Section).
Operating Modes: Multiplexed Control vs. Direct
Control
The DCP can be operated in either of two basic interfacing
modes, determined by the logic level on the C/K input pin. In
Multiplexed Control Mode (C/K LOW), the DCP is internally
connected to allow a host CPU to directly address six
internal (Mode, Command, Status, Mask, Input, Output)
registers and thereby control the device by writing and
reading these registers. In Multiplexed Control Mode, the
Auxiliary Port is also enabled for entering keys.
If the logic level of C/K is brought HIGH, the DCP enters
Direct Control Mode, and the Auxiliary Port pins are
converted into direct hardware control or status signals that
are capable of instructing the DCP to perform a functionally
complete subset of its cipher processing at very high
throughputs. This operating mode is especially well suited
for ciphering data for high-speed peripheral devices.
Initialization
The DCP can be reset in several ways:
1)
By the “Software Reset” command,
2)
By a hardware reset:
(CA95C68) Assertion of
and
LOW
simultaneously for 3 clock cycles,
(CA95C18) Assertion of
and
LOW
simultaneously for 1 clock cycle.
3)
By writing to the Mode Register,
4)
By aborting any command.
MRD
MWR
MAS
MDS
The design of the DCP, as shown in Figure 3-1 is optimized
for high data throughput. The cryptography key bytes can be
written through both the Auxiliary and Master Ports. Three
56-bit, write-only key registers are provided for the Master
(M) Key, the Encryption (E) Key and the Decryption (D)
Key. Parity checking is provided on each incoming key byte.
Two 64-bit registers are provided for the initialization
Vectors (IVE and IVD) required for chained (feedback)
ciphering modes. Clear and cipher data bytes can be
transferred through both the Master and Slave Ports to the
Input Register; conversely, data can be transferred from the
Output Register to either port. Four 8-bit registers (Mode,
Command, Status and Mask) are accessible through the
Master Port for interfacing to a host microprocessor.
Algorithm Processing
The DCP's Algorithm Processing Unit (see Figure 3-1) is
designed to encrypt and decrypt data according to the
National Bureau of Standards Data Encryption Standard
(DES), as specied in Federal Information Processing
Standards Publication FIPS PUB 46 (1-15-1977).
The DES species a method for encrypting 64-bit blocks of
clear data (plain text) into corresponding 64-bit blocks of
cipher text. The DCP offers four ciphering methods:
Electronic Code Book (ECB), Cipher Block Chaining
(CBC), one (CFB-1) and eight bit Cipher Feedback (CFB-8).
Electronic
Code
Block
(ECB)
is
a
straightforward
implementation of the DES algorithm; 64 bits of clear data
in, 64 bits of cipher text out, with no cryptographic
dependence between blocks. Cipher Block Chaining (CBC)
also operates on blocks of 64 bits, but includes a feedback
step which chains consecutive blocks so that repetitive data
in the plain text (such as ASCII blanks) does not yield
identical cipher text. CBC also provides an error extension
characteristic
which
protects
against
fraudulent
data
insertions and deletions. Cipher Feedback is an additive
stream cipher method in which the DES generates a pseudo
random binary stream which is then exclusive-ORed with the
clear text to form the cipher text. The cipher text is then fed
back to form a portion of the next DES input block. The DCP
implements both 1-bit and 8-bit cipher feedback which is
useful
for
low
speed
bit
and
byte
oriented
serial
communications.
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