参数资料
型号: CAP004DG-TL
厂商: POWER INTEGRATIONS INC
元件分类: 模拟信号调理
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO8
封装: GREEN, PLASTIC, MS-012, SOP-8
文件页数: 3/8页
文件大小: 642K
代理商: CAP004DG-TL
Rev. C 04/11
3
CAPZero Family
www.powerint.com
Key Application Considerations
Breakdown Voltage Selection
Figure 3 illustrates possible system configurations influencing
the choice of CAPZero breakdown voltage. The system
configuration variables include the placement of the system
MOV and X capacitor(s) as well as the differential surge voltage
specifications of the application.
As shown in Table 1, each device in the CAPZero family has a
825 V or 1000 V option. For applications where the system
MOV is placed in position 1 (MOV
POS1 in Figure 3), the 825 V
option will typically provide adequate voltage withstand for
surge requirements up to 3 kV or more. The 1 kV CAPZero
would be recommended for higher surge requirements or if
additional voltage margin is required.
For MOV placement that is not directly across the X Capacitor1
(for example MOV
POS2 in Figure 3) the 1000 V CAPZero devices
can be used up to a surge specification of 1.5 kV. For differential
surge voltage specifications of >1.5 kV it is recommended that
the MOV is always placed in the location shown in Figure 3 as
MOV
POS1.
It is always recommended that the peak voltage between
terminals D1 and D2 of CAPZero is measured during surge
tests in the final system. Measurements of peak voltage across
CAPZero during surge tests should be made with oscilloscope
probes having appropriate voltage rating and using an isolated
supply to the oscilloscope to avoid ground currents influencing
measurement results. When making such measurements, it is
recommended that 50 V engineering margin is allowed below
the breakdown voltage specification (for example 950 V with the
1000 V CAPZero).
Figure 3.
Placement Options of MOV and C
EXT.
If the measured peak Drain voltage exceeds 950 V, an external
1 kV ceramic capacitor of value up to 47 pF can also be placed
between D1 and D2 terminals to attenuate the voltage applied
between the CAPZero terminals during surge. This optional
external capacitor placement is shown as C
EXT in Figure 3. It
should be noted that use of an external capacitor in this way will
increase power consumption slightly due to the C
EXT charge/
discharge currents flowing in R1 and R2 while AC is connected.
A C
EXT value of 33 pF will add approximately 0.5 mW at 230 VAC,
50 Hz.
PCB Layout and External Resistor Selection
Figure 4 shows a typical PCB layout configuration for CAPZero.
The external resistors in this case are divided into two separate
surface mount resistors to distribute loss under fault conditions
– for example where a short-circuit exists between CAPZero
terminals D1 and D2. R1 and R2 values are selected according
to Table 1.
Under a fault condition where CAPZero terminals D1 and D2 are
shorted together, each resistor will dissipate a power that can
be calculated from the applied AC voltage and the R1 and R2
values. For example in an application using CAP004 or CAP014,
R1=R2=390 kW. If CAPZero is shorted out at 265 VAC R1 and
R2 will each dissipate 45 mW.
Resistors R1 and R2 should also be rated for 50% of the system
input voltage again to allow for the short-circuitry of CAPZero
D1 to D2 pins during single point fault testing.
If lower dissipation or lower voltage across each resistor is
required during fault tests, the total external resistance can be
divided into more discrete resistors, however the total resistance
must be equal to that specified in Table 1.
PI-5609-041210
D1
R1
R2
X Capacitor1
CEXT
AC
X Capacitor2
MOVPOS1
MOVPOS2
CAPZero
D2
Other EMI
Filter
Components
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