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| 型号： | CAT1023WI-28-T3 |
| 厂商： | ON Semiconductor |
| 文件页数： | 5/20页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR W/MEM 2.85V 8SOIC |
| 标准包装： | 1 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 高有效/低有效 |
| 复位超时： | 最小为 130 ms |
| 电压 - 阀值： | 2.85V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 标准包装 |
| 产品目录页面： | 806 (CN2011-ZH PDF) |
| 其它名称： | CAT1023WI-28-T3DKR |
CAT1021, CAT1022, CAT1023
Table 6. D.C. OPERATING CHARACTERISTICS
V CC = 2.7 V to 5.5 V and over the recommended temperature conditions unless otherwise specified.
Symbol
V TH
Parameter
Reset Threshold
Test Conditions
CAT102x ? 45
(V CC = 5.0 V)
Min
4.50
Typ
Max
4.75
Units
V
CAT102x ? 42
(V CC = 5.0 V)
CAT102x ? 30
(V CC = 3.3 V)
CAT102x ? 28
(V CC = 3.3 V)
CAT102x ? 25
(V CC = 3.0 V)
4.25
3.00
2.85
2.55
4.50
3.15
3.00
2.70
V RVALID
V RT (Note 4)
Reset Output Valid V CC Voltage
Reset Threshold Hysteresis
1.00
15
V
mV
3. V IL min and V IH max are reference values only and are not tested.
4. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
Table 7. CAPACITANCE
T A = 25 ° C, f = 1.0 MHz, V CC = 5 V
Symbol
C OUT (Note 5)
C IN (Note 5)
Output Capacitance
Input Capacitance
Test
Test Conditions
V OUT = 0 V
V IN = 0 V
Max
8
6
Units
pF
pF
Table 8. AC CHARACTERISTICS
V CC = 2.7 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle (Note 6)
Symbol
Parameter
Min
Max
Units
f SCL
t SP
t LOW
t HIGH
t R (Note 5)
t F (Note 5)
t HD; STA
t SU; STA
t HD; DAT
t SU; DAT
t SU; STO
t AA
t DH
t BUF (Note 5)
t WC (Note 7)
Clock Frequency
Input Filter Spike Suppression (SDA, SCL)
Clock Low Period
Clock High Period
SDA and SCL Rise Time
SDA and SCL Fall Time
Start Condition Hold Time
Start Condition Setup Time (for a Repeated Start)
Data Input Hold Time
Data Input Setup Time
Stop Condition Setup Time
SCL Low to Data Out Valid
Data Out Hold Time
Time the Bus must be Free Before a New Transmission Can Start
Write Cycle Time (Byte or Page)
1.3
0.6
0.6
0.6
0
100
0.6
50
1.3
400
100
300
300
900
5
kHz
ns
m s
m s
ns
ns
m s
m s
ns
ns
m s
ns
ns
m s
ms
5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
6. Test Conditions according to “AC Test Conditions” table.
7. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
http://onsemi.com
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