参数资料
型号: CAT1025ZI-42-GT3
厂商: ON Semiconductor
文件页数: 10/20页
文件大小: 0K
描述: IC SUPERVISOR CPU 2K EEPR 8MSOP
标准包装: 3,000
类型: 简单复位/加电复位
监视电压数目: 1
输出: 开路漏极或开路集电极
复位: 高有效/低有效
复位超时: 最小为 130 ms
电压 - 阀值: 4.25V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: 8-MSOP
包装: 带卷 (TR)
CAT1024, CAT1025
ACKNOWLEDGE
After a successful data transfer, each receiving
device is required to generate an acknowledge. The
acknowledging device pulls down the SDA line
during the ninth clock cycle, signaling that it received
the 8 bits of data.
The CAT1024/25 responds with an acknowledge
after receiving a START condition and its slave
address. If the device has been selected along with
a write operation, it responds with an acknowledge
after receiving each 8-bit byte.
When the CAT1024/25 begins a READ mode it
transmits 8 bits of data, releases the SDA line and
monitors the line for an acknowledge. Once it
receives this acknowledge, the CAT1024/25 will
continue to transmit data. If no acknowledge is sent
by the Master, the device terminates data transmis–
sion and waits for a STOP condition.
Figure 5. Start/Stop Timing
SDA
SCL
START BIT
Figure 6. Acknowledge Timing
WRITE OPERATIONS
Byte Write
ˉ ˉ
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
a 8-bit address that is to be written into the address
pointers of the device. After receiving another acknow-
ledge from the Slave, the Master device transmits the
data to be written into the addressed memory location.
The CAT1024/25 acknowledges once more and the
Master generates the STOP condition. At this time, the
device begins an internal programming cycle to non-
volatile memory. While the cycle is in progress,
the device will not respond to any request from the
Master device.
STOP BIT
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
Figure 7: Slave Address Bits
START
ACKNOWLEDGE
Default Configuration
1
0
1
0
0
0
0
R/W
Doc. No. MD-3008 Rev. R
10
? 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
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