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参数资料
| 型号： | CAT1025ZI-45-GT3 |
| 厂商： | ON Semiconductor |
| 文件页数： | 13/20页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR CPU 2K EEPR 8MSOP |
| 标准包装： | 3,000 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 高有效/低有效 |
| 复位超时： | 最小为 130 ms |
| 电压 - 阀值： | 4.5V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-MSOP |
| 包装： | 带卷 (TR) |
CAT1024, CAT1025
Immediate/Current Address Read
ˉ ˉ
The CAT1024 and CAT1025 address counter
contains the address of the last byte accessed,
incremented by one. In other words, if the last READ
or WRITE access was to address N, the READ
immediately following would access data from
address N + 1. For N = E = 255, the counter will
wrap around to zero and continue to clock out valid
data. After the CAT1024/1025 receives its slave
address information (with the R/W bit set to one), it
issues an acknowledge, then transmits the 8-bit byte
requested. The master device does not send an
acknowledge, but will generate a STOP condition.
Selective/Random Read
ˉ ˉ
Selective/Random READ operations allow the
Master device to select at random any memory
location for a READ operation. The Master device
first performs a ‘dummy’ write operation by sending
the START condition, slave address and byte
addresses of the location it wishes to read. After the
CAT1024 and CAT1025 acknowledges, the Master
device sends the START condition and the slave
address again, this time with the R/W bit set to one.
The CAT1024 and CAT1025 then responds with its
acknowledge and sends the 8-bit byte requested.
The master device does not send an acknowledge
but will generate a STOP condition.
Figure 11. Selective Read Timing
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT1024 and CAT1025 sends the
inital 8-bit byte requested, the Master will responds with
an acknowledge which tells the device it requires more
data. The CAT1024 and CAT1025 will continue to
output an 8-bit byte for each acknowledge, thus sending
the STOP condition.
The data being transmitted from the CAT1024 and
CAT1025 is sent sequentially with the data from
address N followed by data from address N + 1. The
READ operation address counter increments all of the
CAT1024 and CAT1025 address bits so that the entire
memory array can be read during one operation.
BUS ACTIVITY:
MASTER
S
T
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS (n)
S
T
A
R
T
SLAVE
ADDRESS
S
T
O
P
SDA LINE
S
S
P
A
C
K
A
C
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A
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DATA n
N
O
A
C
K
Figure 12. Sequential Read Timing
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
S
T
O
P
SDA LINE
P
? 2009 SCILLC. All rights reserved.
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Doc. No. MD-3008 Rev. R
Characteristics subject to change without notice
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| CAT1025ZI-45-T3 | 功能描述:监控电路 CPU w/2K RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
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| CAT1026LI25 | 功能描述:监控电路 2K bit 2.5V Ind Temp RoHS:否 制造商:STMicroelectronics 监测电压数: 监测电压: 欠电压阈值: 过电压阈值: 输出类型:Active Low, Open Drain 人工复位:Resettable 监视器:No Watchdog 电池备用开关:No Backup 上电复位延迟（典型值）:10 s 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:UDFN-6 封装:Reel |
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