参数资料
型号: CAT1027ZI-30-GT3
厂商: ON Semiconductor
文件页数: 6/19页
文件大小: 0K
描述: IC SUPERVISOR CPU 2K EEPR 8MSOP
标准包装: 3,000
类型: 多压监控器
监视电压数目: 2
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小为 130 ms
电压 - 阀值: 3V,可调
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: 8-MSOP
包装: 带卷 (TR)
CAT1026, CAT1027
Table 9. RESET CIRCUIT AC CHARACTERISTICS
Symbol
t PURST
t RDP
t GLITCH
t WD
t RPD2
Parameter
Power ? Up Reset Timeout
V TH to RESET output Delay
V CC Glitch Reject Pulse Width
Watchdog Timeout
V SENSE to V LOW Delay
Test Conditions
Note 2
Note 3
Notes 4 and 5
Note 1
Note 5
Min
130
1.0
Typ
200
1.6
Max
270
5
30
2.1
5
Units
ms
m s
ns
s
m s
Table 10. POWER ? UP TIMING (Notes 6 and 7)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
t PUR
t PUW
Power ? Up to Read Operation
Power ? Up to Write Operation
270
270
ms
ms
Table 11. AC TEST CONDITIONS
Parameter
Input Pulse Voltages
Input Rise and Fall Times
Input Reference Voltages
Output Reference Voltages
Output Load
Table 12. RELIABILITY CHARACTERISTICS
Test Conditions
0.2 x V CC to 0.8 x V CC
10 ns
0.3 x V CC , 0.7 x V CC
0.5 x V CC
Current Source: I OL = 3 mA; C L = 100 pF
Symbol
N END (Note 6)
T DR (Note 6)
V ZAP (Note 6)
I LTH (Notes 6 & 8)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch ? Up
Reference Test Method
MIL ? STD ? 883, Test Method 1033
MIL ? STD ? 883, Test Method 1008
MIL ? STD ? 883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Max
Units
Cycles/Byte
Years
Volts
mA
1.
2.
3.
4.
5.
6.
7.
8.
Test Conditions according to “AC Test Conditions” table.
Power ? up, Input Reference Voltage V CC = V TH , Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
Power ? Down, Input Reference Voltage V CC = V TH , Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
V CC Glitch Reference Voltage = V THmin ; Based on characterization data
0 < V SENSE ? V CC , V LOW Output Reference Voltage and Load according to “AC Test Conditions” Table.
This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
t PUR and t PUW are the delays required from the time V CC is stable until the specified memory operation can be initiated.
Latch ? up protection is provided for stresses up to 100 mA on input and output pins from ? 1 V to V CC + 1 V.
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