参数资料
| 型号： | CAT1232LPV-T3 |
| 厂商： | ON Semiconductor |
| 文件页数： | 5/12页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR MPU 5V 8SOIC |
| 标准包装： | 1 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极，推挽式 |
| 复位： | 高有效/低有效 |
| 复位超时： | 可调节/可选择 |
| 电压 - 阀值： | 4.37V，4.62V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 标准包装 |
| 其它名称： | CAT1232LPV-T3DKR |
CAT1232LP, CAT1832
APPLICATION INFORMATION
SUPPLY VOLTAGE MONITOR
Reset Signal Polarity and Output Stage Structure
ˉˉˉˉˉˉ
ˉˉˉˉˉˉ
RESET is an active LOW signal. It is developed with
an open drain driver in the CAT1232LP. A pull-up
resistor is required, typical values are 10 k ? to 50 k ? .
The CAT1832 uses a CMOS push-pull output stage
for the RESET .
RESET is an active High signal developed by a
Tolerance
Select
Voltage
CAT1232LP
TOL = V CC
CAT1232LP
TOL = GND
Trip Point
Tolerance
10 %
5%
Trip Point Voltage (V)
Min Nominal Max
4.25 4.37 4.49
4.50 4.62 4.74
ˉˉˉˉˉˉ
CMOS push-pull output stage and is the logical
opposite to RESET .
Trip Point Tolerance Selection
The TOL input is used to select the V CC trip point
CAT1832
TOL = V CC
CAT1832
TOL = GND
20 %
10 %
2.47
2.80
2.55
2.88
2.64
2.97
threshold. This selection is made connecting the
TOL input to ground or V CC . Connecting TOL to
Ground makes the V CC trip threshold 4.62 V for the
CAT1232LP and 2.88 V for the CAT1832.
Connecting TOL to V CC makes the V CC trip threshold
4.37 V for the CAT1232LP and 2.55 V for the
CAT1832.
ˉˉˉˉˉˉ
After V CC has risen above the trip point set by TOL,
RESET and RESET remain active for a minimum time
period of 250 ms.
On power-down, once V CC falls below the reset
threshold the RESET outputs will remain active and
are guaranteed valid down to a V CC level of 1.0 V.
Figure 1. Timing Diagram: Power Up
Manual Reset Operation
ˉˉˉˉˉˉ
Push-button input, PBRST , allows the user to issue
reset signals. The pushbutton input is debounced and
is pulled high through an internal 40 k ? resistor.
ˉˉˉˉˉˉ
When PBRST is held low for the minimum time of
20 ms, both resets become active and remain active
for a minimum time period of 250 ms after PBRST
returns high.
ˉˉˉˉˉˉ
No external pull-up resistor is required, since PBRST
is pulled high by an internal 40 k ? resistor.
ˉˉˉˉˉˉ
PBRST can be driven from a TTL or CMOS logic line
or short-ed to ground with a mechanical switch.
Figure 2. Timing Diagram: Power Down
V CCTP(MIN)
t R
V CCTP(MAX)
V CCTP
V CC
V CCTP(MAX)
V CCTP
t F
V CCTP(MIN)
V CC
t RPU
RESET
RESET
t RPD
V OH
V OH
? 2009 SCILLC. All rights reserved.
V OL
RESET
5
RESET
V OL
Doc. No. MD-3018 Rev. F
Characteristics subject to change without notice
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