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参数资料
| 型号： | CAT1320YI-45-GT3 |
| 厂商： | ON Semiconductor |
| 文件页数： | 6/18页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR I2C 32K EEPR 8TSSO |
| 标准包装： | 3,000 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 最小为 130 ms |
| 电压 - 阀值： | 4.5V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 带卷 (TR) |
CAT1320, CAT1321
Table 8. RESET CIRCUIT AC CHARACTERISTICS
Symbol
t PURST
Reset Timeout
Parameter
Test Conditions
Note 2
Min
130
Typ
200
Max
270
Units
ms
t RDP
t GLITCH
MR Glitch
t MRW
V TH to RESET output Delay
V CC Glitch Reject Pulse Width
Manual Reset Glitch Immunity
MR Pulse Width
Note 3
Notes 4 and 5
Note 5
Note 5
5
5
30
100
m s
ns
ns
m s
Table 9. POWER ? UP TIMING (Notes 5 and 6)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
t PUR
t PUW
Power ? Up to Read Operation
Power ? Up to Write Operation
270
270
ms
ms
Table 10. AC TEST CONDITIONS
Parameter
Input Pulse Voltages
Input Rise and Fall Times
Input Reference Voltages
Output Reference Voltages
Output Load
Table 11. RELIABILITY CHARACTERISTICS
Test Conditions
0.2 V CC to 0.8 V CC
10 ns
0.3 V CC , 0.7 V CC
0.5 V CC
Current Source: I OL = 3 mA; C L = 100 pF
Symbol
N END (Note 5)
T DR (Note 5)
V ZAP (Note 5)
I LTH (Notes 5 & 7)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch ? Up
Reference Test Method
MIL ? STD ? 883, Test Method 1033
MIL ? STD ? 883, Test Method 1008
MIL ? STD ? 883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Max
Units
Cycles/Byte
Years
Volts
mA
1.
2.
3.
4.
5.
6.
7.
Test Conditions according to “AC Test Conditions” table.
Power ? up, Input Reference Voltage V CC = V TH , Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
Power ? Down, Input Reference Voltage V CC = V TH , Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
V CC Glitch Reference Voltage = V THmin ; Based on characterization data
This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
t PUR and t PUW are the delays required from the time V CC is stable until the specified memory operation can be initiated.
Latch ? up protection is provided for stresses up to 100 mA on input and output pins from ? 1 V to V CC + 1 V.
http://onsemi.com
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