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| 型号： | CAT1320YI-45TDFN |
| 英文描述： | Supervisory Circuits with I2C Serial 32K CMOS EEPROM |
| 中文描述： | 监控电路，带有I2C串行EEPROM中的CMOS 32K的 |
| 文件页数： | 17/18页 |
| 文件大小： | 496K |
| 代理商： | CAT1320YI-45TDFN |
8
CAT1320, CAT1321
Advance Information
Doc. No. 25085, Rev. 00
EMBEDDED EEPROM OPERATION
The CAT1320 and CAT1321 feature a 32kbit
embedded serial EEPROM that supports the I2C Bus
data transmission protocol. This Inter-Integrated
Circuit Bus protocol defines any device that sends
data to the bus to be a transmitter and any device
receiving data to be a receiver. The transfer is
controlled by the Master device which generates the
serial clock and all START and STOP conditions for
bus access. Both the Master device and Slave device
can operate as either transmitter or receiver, but the
Master device controls which mode is activated.
I2C Bus Protocol
The features of the I2C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes in
the data line while the clock line is high will be interpreted
as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT1320/21 monitors the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition. The Master sends the address of the particular
slave device it is requesting. The four most significant
bits of the 8-bit slave address are programmable in metal
and the default is 1010.
The last bit of the slave address specifies whether a
Read or Write operation is to be performed. When this bit
is set to 1, a Read operation is selected, and when set
to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT1320/21 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT1320/21 then performs a Read or Write operation
depending on the R/
W bit.
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK
8TH BIT
BYTE n
SCL
SDA
Figure 4. Write Cycle Timing
相关PDF资料 |
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|---|---|
| CAT1320RD2I-28 | 1-CHANNEL POWER SUPPLY SUPPORT CKT, DSO8 |
| CAT1320UI-45TE13 | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
| CAT1320YI-45 | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
| CAT1320WI-28TE13 | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
| CAT1320ZD2I-30TE13 | 1-CHANNEL POWER SUPPLY SUPPORT CKT, DSO8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CAT1320ZD2I-25-T2 | 制造商:ON Semiconductor 功能描述:CPU SUPERVISOR WITH 32K EEPROM - Tape and Reel |
| CAT1320ZD2I-28-T2 | 制造商:ON Semiconductor 功能描述:CPU SUPERVISOR WITH 32K EEPROM - Tape and Reel |
| CAT1320ZD2I-30-T2 | 制造商:ON Semiconductor 功能描述:CPU SUPERVISOR WITH 32K EEPROM - Tape and Reel |
| CAT1320ZD2I-42-T2 | 制造商:ON Semiconductor 功能描述:CPU SUPERVISOR WITH 32K EEPROM - Tape and Reel |
| CAT1320ZD2I-45-T2 | 制造商:ON Semiconductor 功能描述:CPU SUPERVISOR WITH 32K EEPROM - Tape and Reel |
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