参数资料
型号: CAT140021SWI-GT3
厂商: ON Semiconductor
文件页数: 8/11页
文件大小: 0K
描述: IC SUPERVISOR I2C 2K EEPR 8SOIC
标准包装: 3,000
类型: 简单复位/加电复位
监视电压数目: 1
输出: 推挽式,图腾柱
复位: 高有效
复位超时: 最小为 140 ms
电压 - 阀值: 2.93V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
CAT140xx
transmitted the CAT140xx will respond with an
acknowledge and internally increments the four low order
address bits. The high order bits that define the page address
remain unchanged. If the Master transmits more than sixteen
bytes prior to sending the STOP condition, the address
counter ‘wraps around’ to the beginning of page and
previously transmitted data will be overwritten. Once all
sixteen bytes are received and the STOP condition has been
sent by the Master, the internal Write cycle begins. At this
point all received data is written to the CAT140xx in a single
write cycle.
Acknowledge Polling
The acknowledge (ACK) polling routine can be used to
take advantage of the typical write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation, the CAT140xx initiates the internal write cycle.
The ACK polling can be initiated immediately. This
involves issuing the start condition followed by the slave
address for a write operation. If the CAT140xx is still busy
with the write operation, NoACK will be returned. If the
CAT140xx has completed the internal write operation, an
ACK will be returned and the host can then proceed with the
next read or write operation.
BUS ACTIVITY:
MASTER
S
T
A
R
T
SLAVE
ADDRESS
ADDRESS
BYTE
a7 ? a0
DATA
BYTE
d7 ÷ d0
S
T
O
P
S
P
SLAVE
A
C
K
A
C
K
A
C
K
Figure 7. Byte Write Sequence
SCL
SDA
8th Bit
Byte n
ACK
tWR
BUS
STOP
CONDITION
Figure 8. Write Cycle Timing
START
CONDITION
ADDRESS
ACTIVITY:
S
T
DATA
DATA
DATA
S
MASTER
A
R
T
SLAVE
ADDRESS
ADDRESS
BYTE
BYTE
n
BYTE
n+1
BYTE
n+P
T
O
P
S
P
SLAVE
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
n=1
P ≤ 15
Figure 9. Page Write Timing
http://onsemi.com
8
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