参数资料
型号: CAT140049SWI-GT3
厂商: ON Semiconductor
文件页数: 6/14页
文件大小: 0K
描述: IC SUPERVISOR I2C EEPROM 8SOIC
标准包装: 3,000
类型: 简单复位/加电复位
监视电压数目: 1
输出: 推挽式,图腾柱
复位: 低有效
复位超时: 最小为 140 ms
电压 - 阀值: 2.93V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
其它名称: 140049SWI-GT3
CAT140xx
EMBEDDED EEPROM OPERATION
The CAT140xx supports the Inter-Integrated Circuit
(I 2 C) Bus data transmission protocol, which defines a
device that sends data to the bus as a transmitter and
a device receiving data as a receiver. Data flow is
controlled by a Master device, which generates the
serial clock and all START and STOP conditions. The
CAT140xx acts as a Slave device. Master and Slave
alternate as either transmitter or receiver.
I 2 C BUS PROTOCOL
The I 2 C bus consists of two ‘wires’, SCL and SDA.
The two wires are connected to the V CC supply via
pull-up resistors. Master and Slave devices connect to
the 2-wire bus via their respective SCL and SDA pins.
The transmitting device pulls down the SDA line to
‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
STOP
The STOP condition completes all commands.
It consists of a LOW to HIGH transition on SDA while
SCL is HIGH. The STOP starts the internal Write cycle
(when following a Write command) or sends the
Slave into standby mode (when following a Read
command).
Device Addressing
The Master initiates data transfer by creating a
START condition on the bus. The Master then
broadcasts an 8-bit serial Slave address. For normal
Read/Write operations, the first 4 bits of the Slave
address are fixed at 1010 (Ah). The next 3 bits are
used as programmable address bits when cascading
multiple devices and/or as internal address bits. The
last bit of the slave address, R/W, specifies whether a
Read (1) or Write (0) operation is to be performed.
The 3 address space extension bits are assigned as
illustrated in Figure 4. A 2 , A 1 and A 0 must match the
state of the external address pins, and a 10 , a 9 and a 8
are internal address bits.
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while
SCL is HIGH will be interpreted as a START or STOP
condition (Figure 3). The START condition precedes
all commands. It consists of a HIGH to LOW transition
on SDA while SCL is HIGH. The START acts as a
‘wake-up’ call to all receivers. Absent a START, a
Slave will not respond to commands. The STOP
condition completes all commands. It consists of a
LOW to HIGH transition on SDA while SCL is HIGH.
START
The START condition precedes all commands.
It consists of a HIGH to LOW transition on SDA while
SCL is HIGH. The START acts as a ‘wake-up’ call to
all receivers. Absent a START, a Slave will not
respond to commands.
Acknowledge
After processing the Slave address, the Slave
responds with an acknowledge (ACK) by pulling down
the SDA line during the 9 th clock cycle (Figure 5). The
Slave will also acknowledge the address byte and
every data byte presented in Write mode. In Read
mode the Slave shifts out a data byte, and then
releases the SDA line during the 9 th clock cycle. As
long as the Master acknowledges the data, the Slave
will continue transmitting. The Master terminates the
session by not acknowledging the last data byte
(NoACK) and by issuing a STOP condition. Bus timing
is illustrated in Figure 6.
Doc. No. MD-1117 Rev. B
6
? 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
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