- 您现在的位置：买卖IC网 > PDF目录298899 > CAT22C10JA-30 (ON SEMICONDUCTOR) 64 X 4 NON-VOLATILE SRAM, 300 ns, PDSO16 PDF资料下载
参数资料
| 型号： | CAT22C10JA-30 |
| 厂商： | ON SEMICONDUCTOR |
| 元件分类： | SRAM |
| 英文描述： | 64 X 4 NON-VOLATILE SRAM, 300 ns, PDSO16 |
| 封装： | SOIC-16 |
| 文件页数： | 7/10页 |
| 文件大小： | 68K |
| 代理商： | CAT22C10JA-30 |
CAT22C10
6
Doc. No. 1082, Rev. O
DEVICE OPERATION
The configuration of the CAT22C10 allows a common
address bus to be directly connected to the address
inputs. Additionally, the Input/Output (I/O) pins can be
directly connected to a common I/O bus if the bus has
less than 1 TTL load and 100pF capacitance. If not, the
I/O path should be buffered.
When the chip select (
CS) pin goes low, the device is
activated. When CS is forced high, the device goes into
the standby mode and consumes very little current. With
the nonvolatile functions inhibited, the device operates
like a Static RAM. The Write Enable (
WE) pin selects a
write operation when
WE is low and a read operation
when
WE is high. In either of these modes, an array byte
(4 bits) can be addressed uniquely by using the address
lines (A0–A5), and that byte will be read or written to
through the Input/Output pins (I/O0–I/O3).
The nonvolatile functions are inhibited by holding the
STORE input and the RECALL input high. When the
RECALL input is taken low, it initiates a recall operation
which transfers the contents of the entire EEPROM
array into the Static RAM. When the
STORE input is
taken low, it initiates a store operation which transfers
the entire Static RAM array contents into the EEPROM
array.
Standby Mode
The chip select (
CS) input controls all of the functions of
the CAT22C10. When a high level is supplied to the
CS
pin, the device goes into the standby mode where the
outputs are put into a high impendance state and the
power consumption is drastically reduced. With ISB less
than 100
A in standby mode, the designer has the
flexibility to use this part in battery operated systems.
Read
When the chip is enabled (
CS = low), the nonvolatile
functions are inhibited (
STORE = high and RECALL =
high). With the Write Enable (
WE) pin held high, the data
in the Static RAM array may be accessed by selecting an
address with input pins A0–A5. This will occur when the
outputs are connected to a bus which is loaded by no more
than 100pF and 1 TTL gate. If the loading is greater than
this, some additional buffering circuitry is recommended.
Figure 1. Read Cycle Timing
ADDRESS
CS
DATA I/O
tRC
tCO
tAA
tLZ
tOH
tHZ
HIGH-Z
DATA VALID
相关PDF资料 |
PDF描述 |
|---|---|
| CAT22C10J-20 | 64 X 4 NON-VOLATILE SRAM, 200 ns, PDSO16 |
| CAT22C10PA-20 | NVRAM (EEPROM Based) |
| CAT22C10PA-30 | NVRAM (EEPROM Based) |
| CAT22C10PI-20 | NVRAM (EEPROM Based) |
| CAT22C10PI-30 | NVRAM (EEPROM Based) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CAT22C10JA-30TE13 | 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:256-Bit Nonvolatile CMOS Static RAM |
| CAT22C10JA-30-TE13 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:NVRAM (EEPROM Based) |
| CAT22C10JI-20 | 功能描述:NVRAM 256bit (64x4) 5V RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| CAT22C10JI-20TE13 | 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:256-Bit Nonvolatile CMOS Static RAM |
| CAT22C10JI-20-TE13 | 制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:256-Bit Nonvolatile CMOS Static RAM |
发布紧急采购，3分钟左右您将得到回复。