参数资料
| 型号： | CAT24C128YI-G |
| 厂商： | ON Semiconductor |
| 文件页数： | 3/16页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 128KBIT 400KHZ 8TSSOP |
| 标准包装： | 100 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 128K (16K x 8) |
| 速度： | 400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 管件 |
CAT24C128
Table 5. D.C. OPERATING CHARACTERISTICS ? New Product (Rev C) (Note 7)
(V CC = 1.8 V to 5.5 V, T A = ? 40 ° C to +85 ° C and V CC = 2.5 V to 5.5 V, T A = ? 40 ° C to +125 ° C, unless otherwise speci ? ed.)
Symbol
I CCR
I CCW
Parameter
Read Current
Write Current
Test Conditions
Read, f SCL = 400 kHz/1 MHz
Min
Max
1
3
Units
mA
mA
I SB
Standby Current
All I/O Pins at GND or V CC
T A = ? 40 ° C to +85 ° C
2
m A
T A = ? 40 ° C to +125 ° C
5
I L
I/O Pin Leakage
Pin at GND or V CC
T A = ? 40 ° C to +85 ° C
1
m A
T A = ? 40 ° C to +125 ° C
2
V IL1
V IL2
V IH1
V IH2
V OL1
V OL2
Input Low Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
2.5 V ≤ V CC ≤ 5.5 V
1.8 V ≤ V CC < 2.5 V
2.5 V ≤ V CC ≤ 5.5 V
1.8 V ≤ V CC < 2.5 V
V CC ≥ 2.5 V, I OL = 3.0 mA
V CC < 2.5 V, I OL = 1.0 mA
? 0.5
? 0.5
0.7 V CC
0.75 V CC
0.3 V CC
0.25 V CC
V CC + 0.5
V CC + 0.5
0.4
0.2
V
V
V
V
V
V
Table 6. PIN IMPEDANCE CHARACTERISTICS ? New Product (Rev C) (Note 7)
(V CC = 1.8 V to 5.5 V, T A = ? 40 ° C to +85 ° C and V CC = 2.5 V to 5.5 V, T A = ? 40 ° C to +125 ° C, unless otherwi se speci ? ed.)
Symbol
C IN (Note 8)
C IN (Note 8)
I WP , I A (Note 9)
Parameter
SDA I/O Pin Capacitance
Input Capacitance (other pins)
WP Input Current, Address Input
Current (A 0 , A 1 , A 2 )
Conditions
V IN = 0 V
V IN = 0 V
V IN < V IH , V CC = 5.5 V
V IN < V IH , V CC = 3.3 V
Max
8
6
75
50
Units
pF
pF
m A
V IN < V IH , V CC = 1.8 V
V IN > V IH
25
2
7. The product Rev C is identified by letter “C” or dedicated marking code on top of the package.
8. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC ? Q100
and JEDEC test methods.
9. When not driven, the WP, A 0 , A 1 , A 2 pins are pulled down to GND internally. For improved noise immunity, the internal pull ? down is relatively
strong; therefore the external driver must be able to supply the pull ? down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V CC ), the strong pull ? down reverts to a weak current source.
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