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参数资料
| 型号： | CAT24C16ZJ |
| 英文描述： | I2C Serial EEPROM |
| 中文描述： | I2C串行EEPROM的 |
| 文件页数： | 6/7页 |
| 文件大小： | 92K |
| 代理商： | CAT24C16ZJ |
CAT24C01B
6
Doc. No. 25085-00 7/99 S-1
Figure 6. Page Write Timing
Figure5. Byte Write Timing
ing with an acknowledge and by issuing a stop condition.
Refer to Figure 7 for the start word address, read bit,
acknowledge and data transfer sequence.
Sequential Read
The Sequential READ operation can be initiated after
the 24C01B sends the initial 8-bit byte requested, the
Master will respond with an acknowledge which tells the
device it requires more data. The CAT24C01B will
continue to output an 8-bit byte for each acknowledge
sent by the Master. The operation is terminated when
the Master fails to respond with an acknowledge, thus
sending the STOP condition.
The data being transmitted from the CAT24C01B is
output sequentially with data from address N followed by
data from address N+1. The READ operation address
counter increments all of the CAT24C01B address bits
so that the entire memory array can be read during one
operation. If more than bytes are read out, the counter
will “wrap around” and continue to clock out data bytes.
Acknowledge Polling
The disabling of the inputs can be used to take advan-
tage of the typical write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation, the CAT24C01B initiates the internal write
cycle. ACK polling can be initiated immediately. This
involves issuing the start condition followed by the byte
address for a write operation. If the CAT24C01B is still
busy with the write operation, no ACK will be returned.
If the CAT24C01B has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
READ OPERATIONS
The READ operation for the CAT24C01B is initiated in
the same manner as the write operation with the one
exception that the R/
W bit is set to a one. Two different
READ operations are possible: Byte READ and Se-
quential READ.
It should be noted that the ninth clock cycle of the read
operation is not a "don't care." To terminate a read
operation, the master must either issure a stop condition
during the ninth cycle or hold SDA HIGH during the ninth
clock cycle and then issue a stop condition.
Byte Read
To initiate a read operation, the master sends a start
condition followed by a seven bit word address and a
read bit. The CAT24C01B responds with an acknowl-
edge and then transmits the eight bits of data. The read
operation is terminated by the master; by not respond-
BUS ACTIVITY:
SDA LINE
DATA n+3
A
C
K
A
C
K
DATA n
S
T
O
P
S
A
C
K
DATA n+1
A
C
K
S
T
A
R
T
P
WORD
ADDRESS(n)
M
S
B
L
S
B
R
/
W
BUS ACTIVITY:
SDA LINE
A
C
K
A
C
K
DATA n
S
T
O
P
S
T
A
R
T
P
WORD
ADDRESS(n)
M
S
B
L
S
B
R
/
W
BUS ACTIVITY:
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相关代理商/技术参数 |
参数描述 |
|---|---|
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| CAT24C208WI-GT3 | 功能描述:电可擦除可编程只读存储器 8K-Bit Dual Port RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
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| CAT24C21WGI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述: |
| CAT24C21WGI-T3 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述: |
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