参数资料
| 型号： | CAT24C512WI-GT3 |
| 厂商： | ON Semiconductor |
| 文件页数： | 3/16页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 512KB I2C SER 8SOIC |
| 标准包装： | 1 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 512K (64K x 8) |
| 速度： | 100kHz，400kHz，1MHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 标准包装 |
| 其它名称： | CAT24C512WI-GT3OSDKR |
CAT24C512
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Storage Temperature
Voltage on any Pin with Respect to Ground (Note 1)
Ratings
–65 to +150
–0.5 to +6.5
Units
° C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than ? 0.5 V or higher than V CC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than ? 1.5 V or overshoot to no more than V CC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
N END (Notes 3, 4)
T DR
Endurance
Data Retention
Parameter
Min
1,000,000
100
Units
Program/Erase Cycles
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC ? Q100
and JEDEC test methods.
3. Page Mode, V CC = 5 V, 25 ° C.
4. The device uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte
has to be written, 4 bytes (including the ECC bits) are re-programmed. It is recommended to write by multiple of 4 bytes in order to benefit
from the maximum number of write cycles.
Table 3. D.C. OPERATING CHARACTERISTICS
V CC = 1.8 V to 5.5 V, T A = ? 40 ° C to +85 ° C and V CC = 2.5 V to 5.5 V, T A = ? 40 ° C to +125 ° C, unless otherwise speci ? ed.
Symbol
I CCR
I CCW
Parameter
Read Current
Write Current
Test Conditions
Read, f SCL = 400 kHz/1 MHz
V CC = 1.8 V
Min
Max
1
1.8
Units
mA
mA
V CC = 5.5 V
2.5
I SB
Standby Current
All I/O Pins at GND or V CC
T A = ? 40 ° C to +85 ° C
2
m A
T A = ? 40 ° C to +125 ° C
5
I L
I/O Pin Leakage
Pin at GND or V CC
T A = ? 40 ° C to +85 ° C
1
m A
T A = ? 40 ° C to +125 ° C
2
V IL1
V IL2
V IH1
V IH2
V OL1
V OL2
Input Low Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
2.5 V ≤ V CC ≤ 5.5 V
1.8 V ≤ V CC < 2.5 V
2.5 V ≤ V CC ≤ 5.5 V
1.8 V ≤ V CC < 2.5 V
V CC ≥ 2.5 V, I OL = 3.0 mA
V CC < 2.5 V, I OL = 1.0 mA
? 0.5
? 0.5
0.7 V CC
0.75 V CC
0.3 V CC
0.25 V CC
V CC + 0.5
V CC + 0.5
0.4
0.2
V
V
V
V
V
V
Table 4. PIN IMPEDANCE CHARACTERISTICS
V CC = 1.8 V to 5.5 V, T A = ? 40 ° C to +85 ° C and V CC = 2.5 V to 5.5 V, T A = ? 40 ° C to +125 ° C, unless otherwis e speci ? ed.
Symbol
C IN (Note 5)
C IN (Note 5)
I WP , I A (Note 6)
Parameter
SDA I/O Pin Capacitance
Input Capacitance (other pins)
WP Input Current, Address Input
Current (A 0 , A 1 , A 2 )
Conditions
V IN = 0 V
V IN = 0 V
V IN < V IH , V CC = 5.5 V
V IN < V IH , V CC = 3.3 V
Max
8
6
75
50
Units
pF
pF
m A
V IN < V IH , V CC = 1.8 V
V IN > V IH
25
2
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC ? Q100
and JEDEC test methods.
6. When not driven, the WP, A 0 , A 1 , A 2 pins are pulled down to GND internally. For improved noise immunity, the internal pull ? down is relatively
strong; therefore the external driver must be able to supply the pull ? down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V CC ), the strong pull ? down reverts to a weak current source.
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