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参数资料
| 型号： | CAT24WC164LA-REV-F |
| 元件分类： | PROM |
| 英文描述： | 2K X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8 |
| 封装： | GREEN, PLASTIC, DIP-8 |
| 文件页数： | 6/10页 |
| 文件大小： | 410K |
| 代理商： | CAT24WC164LA-REV-F |
CAT24WC164
5
Doc. No. 1026, Rev. I
address pins (A0, A1and A2) can be left floating or
connected to VSS.
The CAT24WC164 can be made compatible with the
CAT24WC16 by tying A2, A1 and A0 to VSS or by
leaving A2, A1 and A0 float.
WP:
Write Protect
If the WP pin is tied to VCC the entire memory array
becomes Write Protected (READ only). When the WP
pin is tied to VSS or left floating normal read/write
operations are allowed to the device.
I2C BUS PROTOCOL
The following defines the features of the I2C bus protocol:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC164 monitor the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The most
significant bit of the 8-bit slave address is fixed as 1. (see
Fig. 5). The next three significant bits (A2, A1, A0) are
the device address bits and define which device or which
part of the device the Master is accessing (The A1 bit
must be the compliment of the A1 input pin signal). Up
to eight CAT24WC164 devices may be individually
addressed by the system. The next three bits are used
as the three most significant bits of the data word
address. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24WC164 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24WC164 then performs a Read or Write operation
depending on the state of the R/
W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowl-
edging device pulls down the SDA line during the ninth
clock cycle, signaling that it received the 8 bits of data.
The CAT24WC164 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
Figure 4. Acknowledge Timing
ACKNOWLEDGE
1
START
SCL FROM
MASTER
89
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CAT24WC16J | 功能描述:电可擦除可编程只读存储器 (2048x8) 16k RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| CAT24WC16J-1.8 | 功能描述:电可擦除可编程只读存储器 (2048x8) 16k RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| CAT24WC16JA | 功能描述:电可擦除可编程只读存储器 (2048x8) 16k RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| CAT24WC16JI | 功能描述:电可擦除可编程只读存储器 (2048x8) 16k RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| CAT24WC16JI-1.8 | 功能描述:电可擦除可编程只读存储器 (2048x8) 16k RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
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