参数资料
型号: CAT25020VE-GT3
厂商: ON Semiconductor
文件页数: 6/18页
文件大小: 0K
描述: IC EEPROM 2KB I2C SER SPI 8SOIC
标准包装: 3,000
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 2K (256 x 8)
速度: 10MHz
接口: SPI 3 线串行
电源电压: 2.5 V ~ 5.5 V
工作温度: -40°C ~ 125°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOICN
包装: 带卷 (TR)
CAT25010, CAT25020, CAT25040
Table 10. STATUS REGISTER
7
1
6
1
5
1
4
1
3
BP1
2
BP0
1
WEL
0
RDY
Table 11. BLOCK PROTECTIO N BITS
Status Register Bits
BP1
0
0
1
1
BP0
0
1
0
1
Array Address Protected
None
CAT25010: 060 ? 07F, CAT25020: 0C0 ? 0FF, CAT25040: 180 ? 1FF
CAT25010: 040 ? 07F, CAT25020: 080 ? 0FF, CAT25040: 100 ? 1FF
CAT25010: 000 ? 07F, CAT25020: 000 ? 0FF, CAT25040: 000 ? 1FF
Protection
No Protection
Quarter Array Protection
Half Array Protection
Full Array Protection
WRITE OPERATIONS
The CAT25010/20/40 device powers up into a write
disable state. The device contains a Write Enable Latch
(WEL) which must be set before attempting to write to the
memory array or to the status register. In addition, the
address of the memory location(s) to be written must be
outside the protected area, as defined by BP0 and BP1 bits
from the status register.
Write Enable and Write Disable
The internal Write Enable Latch and the corresponding
Status Register WEL bit are set by sending the WREN
CS
SCK
instruction to the CAT25010/20/40. Care must be taken to
take the CS input high after the WREN instruction, as
otherwise the Write Enable Latch will not be properly set.
WREN timing is illustrated in Figure 3. The WREN
instruction must be sent prior to any WRITE or WRSR
instruction.
The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 4. Disabling write
operations by resetting the WEL bit, will protect the device
against inadvertent writes.
SI
0
0
0
0
0
1
1
0
SO
Dashed Line = mode (1, 1)
HIGH IMPEDANCE
Figure 3. WREN Timing
CS
SCK
SI
0
0
0
0
0
1
0
0
SO
Dashed Line = mode (1, 1)
HIGH IMPEDANCE
Figure 4. WRDI Timing
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