参数资料
| 型号： | CAT25512VI-GT3 |
| 厂商： | ON Semiconductor |
| 文件页数： | 8/16页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 512KB SPI SER 8-SOIC |
| 标准包装： | 1 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 512K (64K x 8) |
| 速度： | 20MHz |
| 接口： | SPI 3 线串行 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 标准包装 |
| 其它名称： | CAT25512VI-GT3OSDKR |
CAT25512
Write Status Register
The Status Register is written by sending a WRSR
instruction according to timing shown in Figure 7. Only bits
2, 3, 4, 6 and 7 can be written using the WRSR command.
The internal programming for the SR bits will start after
the low to high CS transition. The internal write cycle will
last maximum 5 ms (t WC ).
It is recommended to avoid SR polling routine (through
RDSR) while writing to the status register is in progress
and insert a fixed delay of 5 ms before sending any other
instruction to the CAT25512.
CS
Write Protection
The Write Protect (WP) pin can be used to protect the
Block Protect bits BP0 and BP1 against being inadvertently
altered. When WP is low and the WPEN bit is set to “ 1”,
write operations to the Status Register are inhibited. WP
going low while CS is still low will interrupt a write to the
status register. If the internal write cycle has already been
initiated, WP going low will have no effect on any write
operation to the Status Register. The WP pin function is
blocked when the WPEN bit is set to “0”. The WP input
timing is shown in Figure 8.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
OPCODE
DATA IN
SI
0
0
0
0
0
0
0
1
7
6
5
4
3
2
1
0
MSB
SO
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
Figure 7. WRSR Timing
t WPS
t WPH
CS
SCK
WP
WP
Dashed Line = mode (1, 1)
Figure 8. WP Timing
http://onsemi.com
8
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