参数资料
| 型号： | CAT25640YI-GT3JN |
| 厂商： | ON Semiconductor |
| 文件页数： | 7/19页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM SRL 64KB I2C 8TSSOP |
| 标准包装： | 3,000 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 64K (8K x 8) |
| 速度： | 20MHz |
| 接口： | SPI 3 线串行 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 带卷 (TR) |
CAT25640
Status Register
The Status Register, as shown in Table 10, contains a
number of status and control bits.
The RDY (Ready) bit indicates whether the device is busy
with a write operation. This bit is automatically set to 1 during
an internal write cycle, and reset to 0 when the device is ready
to accept commands. For the host, this bit is read only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is in a
Write Enable state and when set to 0, the device is in a Write
Disable state.
The BP0 and BP1 (Block Protect) bits determine which
blocks are currently write protected. They are set by the user
with the WRSR command and are non ? volatile. The user is
Table 10. STATUS REGISTER
allowed to protect a quarter, one half or the entire memory,
by setting these bits according to Table 11. The protected
blocks then become read ? only.
The WPEN (Write Protect Enable) bit acts as an enable for
the WP pin. Hardware write protection is enabled when the
WP pin is low and the WPEN bit is 1. This condition
prevents writing to the status register and to the block
protected sections of memory. While hardware write
protection is active, only the non ? block protected memory
can be written. Hardware write protection is disabled when
the WP pin is high or the WPEN bit is 0. The WPEN bit, WP
pin and WEL bit combine to either permit or inhibit Write
operations, as detailed in Table 12.
7
WPEN
6
0
5
0
4
0
3
BP1
2
BP0
1
WEL
0
RDY
Table 11. BLOCK PROTECTION BITS
Status Register Bits
BP1
0
0
1
1
BP0
0
1
0
1
Array Address Protected
None
1800 ? 1FFF
1000 ? 1FFF
0000 ? 1FFF
Protection
No Protection
Quarter Array Protection
Half Array Protection
Full Array Protection
Table 12. WRITE PROTECT CONDITIONS
WPEN
0
0
1
1
X
X
WP
X
X
Low
Low
High
High
WEL
0
1
0
1
0
1
Protected Blocks
Protected
Protected
Protected
Protected
Protected
Protected
Unprotected Blocks
Protected
Writable
Protected
Writable
Protected
Writable
Status Register
Protected
Writable
Protected
Protected
Protected
Writable
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