参数资料
型号: CAT34AC02ZE-TE13
元件分类: PROM
英文描述: 256 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8
封装: LEAD AND HALOGEN FREE, MSOP-8
文件页数: 5/10页
文件大小: 68K
代理商: CAT34AC02ZE-TE13
CAT34AC02
4
Doc. No. 1025, Rev. E
FUNCTIONAL DESCRIPTION
The CAT34AC02 supports the SMBus data transmission
protocol. This serial protocol defines any device that
sends data to the bus to be a transmitter and any device
receiving data to be a receiver. Data transfer is controlled
by the Master device which generates the serial clock
and all START and STOP conditions for bus access. The
CAT34AC02 operates as a Slave device. Both the
Master and Slave devices can operate as either
transmitter or receiver, but the Master device controls
which mode is activated. A maximum of 8 devices may
be connected to the bus as determined by the device
address inputs A0, A1, and A2.
PIN DESCRIPTIONS
SCL: Serial Clock
The CAT34AC02 serial clock input pin is used to clock
all data transfers into or out of the device. This is an input
pin.
SDA: Serial Data/Address
The CAT34AC02 bidirectional serial data/address pin is
used to transfer data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed with
other open drain or open collector outputs.
A0, A1, A2: Device Address Inputs
These inputs set device address when cascading multiple
devices. A maximum of eight devices can be cascaded
when using the device.
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. For CAT34AC02 when this pin is tied
to VCC, the entire array of memory is write protected.
When left floating, memory is unprotected.
Figure 3. Start/Stop Timing
Figure 2. Write Cycle Timing
Figure 1. Bus Timing
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA
tDH
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK
8TH BIT
BYTE n
SCL
SDA
START BIT
SDA
STOP BIT
SCL
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