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参数资料
| 型号： | CAT511JI-TE13 |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO14 |
| 封装： | SOIC-14 |
| 文件页数： | 6/9页 |
| 文件大小： | 56K |
| 代理商： | CAT511JI-TE13 |
CAT511
6
Advanced Information
As data transfers are edge triggered clean clock transi-
tions are necessary to avoid falsely clocking data into the
control register. Standard CMOS and TTL logic families
work well in this regard and it is recommended that any
mechanical switches used for breadboarding or device
evaluation purposes be debounced by a flip-flop or other
suitable debouncing circuit.
VREF
VREF, the voltage applied between pins VREFH &VREFL,
sets the DAC’s Zero to Full Scale output range where
VREFL = Zero and VREFH = Full Scale. VREF can span the
full power supply range or just a fraction of it. In typical
applications VREFH &VREFL are connected across the
power supply rails. When using less than the full supply
voltage be mindfull of the limits placed on VREFH and
VREFL as specified in the "References" section of DC
"Electrical Characteristics".
READY/
BUSY
When saving data to non-volatile EEPROM memory, the
Ready/Busy ouput (RDY/
BSY) signals the start and
duration of the EEPROM erase/write cycle. Upon receiv-
ing a command to store data (PROG goes high) RDY/
BSY goes low and remains low until the programming
cycle is complete. During this time the CAT511 will
ignore any data appearing at DI and no data will be
output on DO.
RDY/
BSY is internally ANDed with a low voltage detec-
tor circuit monitoring VDD. If VDD is below the minimum
value required for EEPROM programming, RDY/
BSY
will remain high following the program command indicat-
ing a failure to record the desired data in non-volatile
memory.
DATA OUTPUT
Data is output serially by the CAT511, LSB first, via the
Data Out (DO) pin following the reception of a start bit
and two address bits by the Data Input (DI).
DO
becomes active whenever CS goes high and resumes
its high impedance Tri-State mode when CS returns low.
Tri-Stating the DO pin allows several 511s to share a
single serial data line and simplifies interfacing multiple
511s to a microprocessor.
WRITING TO MEMORY
Programming the CAT511’s EEPROM memory is ac-
complished through the control signals: Chip Select
(CS) and Program (PROG). With CS high, a start bit
followed by a two bit DAC address and eight data bits are
clocked into the DAC control register via the DI pin. Data
enters on the clock’s rising edge.
The DAC output
changes to its new setting on the clock cycle following
D7, the last data bit.
Programming is accomplished by bringing PROG high
sometime after the start bit and at least 150 ns prior to the
rising edge of the clock cycle immediately following the
D7 bit. Two clock cycles after the D7 bit the DAC control
register will be ready to receive the next set of address
and data bits. The clock must be kept running through-
out the programming cycle. Internal control circuitry
takes care of generating and ramping up the program-
ming voltage for data transfer to the EEPROM cells. The
CAT511’s EEPROM memory cells will endure over
1,000,000 write cycles and will retain data for a minimum
of 100 years without being refreshed.
READING DATA
Each time data is transferred into the DAC control
register currently held data is shifted out via the D0 pin,
thus in every data transaction a read cycle occurs. Note,
however, that the reading process is destructive. Data
must be removed from the register in order to be read.
Figure 2 depicts a Read Only cycle in which no change
occurs in the DAC’s output. This feature allows
Ps to
poll DACs for their current setting without disturbing the
output voltage but it assumes that the setting being read
is also stored in EEPROM so that it can be restored at the
end of the read cycle. In Figure 2 CS returns low before
the 13th clock cycle completes. In doing so the EEPROM’s
Figure 1. Writing to Memory
Figure 2. Reading from Memory
A0
A1
1
DO
DI
CS
PROG
DAC
OUTPUT
t
1
2
3
4
5
6
7
8
9
10
11
12
o
CURRENT
DAC VALUE
NON-VOLATILE
D0
D1
D2
D3
D4
D5
D6
D7
CURRENT DAC DATA
RDY/BSY
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
D0
D1
D2
D3
D4
D5
D6
D7
1
NEW DAC DATA
CURRENT DAC DATA
CURRENT
DAC VALUE
NON-VOLATILE
DAC
OUTPUT
PROG
DO
DI
CS
NEW
DAC VALUE
VOLATILE
NEW
DAC VALUE
NON-VOLATILE
t
1
2
3
4
5
6
7
8
9
10
11
12
N
N+1 N+2
o
RDY/BSY
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