参数资料
型号: CAT5171TBI-50GT3
厂商: ON Semiconductor
文件页数: 12/12页
文件大小: 0K
描述: IC POT DGTL 50K 256TAP SOT23-8
标准包装: 3,000
接片: 256
电阻(欧姆): 50k
电路数: 1
温度系数: 标准值 100 ppm/°C
存储器类型: 易失
接口: I²C(设备位址)
电源电压: 2.7 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: SOT-23-8
供应商设备封装: SOT-23-8
包装: 带卷 (TR)
CAT5171
http://onsemi.com
9
I2C BUS PROTOCOL
The following defines the features of the I2C bus protocol:
1. Data transfer may be initiated only when the bus is
not busy.
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock is high
will be interpreted as a START or STOP condition.
The device controlling the transfer is a master, typically a
processor or controller, and the device being controlled is the
slave. The master will always initiate data transfers and
provide the clock for both transmit and receive operations.
Therefore, the CAT5171 will be considered a slave device
in all applications.
START Condition
The START condition precedes all commands to the
device, and is defined as a high to low transition of SDA
when SCL is high. The CAT5171 monitors the SDA and
SCL lines and will not respond until this condition is met.
STOP Condition
A low to high transition of SDA when SCL is high
determines the STOP condition. All operations must end
with a STOP condition.
Device Addressing
The bus Master begins a transmission by sending a
START condition. The Master then sends the address of the
particular slave device it is requesting. The six most
significant bits of the 8-bit slave address are fixed as 010110
for the CAT5171. The next bit (AD0) is the device least
significant address bit and defines which device the Master
is accessing. Up to two devices may be individually
addressed by the system. Typically, +5 V (VDD) or ground
is hard-wired to the AD0 pin to establish the device’s
address.
After the Master sends a START condition and the slave
address byte, the CAT5171 monitors the bus and responds
with an acknowledge (on the SDA line) when its address
matches the transmitted slave address.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledging
device pulls down the SDA line during the ninth clock cycle,
signaling that it received the 8 bits of data.
The CAT5171 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8-bit
byte.
When the CAT5171 is in a READ mode it transmits 8 bits
of data, releases the SDA line, and monitors the line for an
acknowledge. Once it receives this acknowledge, the
CAT5171 will continue to transmit data. If no acknowledge
is sent by the Master, the device terminates data transmission
and waits for a STOP condition.
Write Operation
In the Write mode, the Master device sends the START
condition and the slave address information to the Slave
device. After the Slave generates an acknowledge, the
Master sends the instruction byte. After receiving another
acknowledge from the Slave, the Master device transmits
the data to be written into the wiper register. The CAT5171
acknowledges once more and the Master generates the
STOP condition.
Figure 15. Bus Timing Diagram
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA
tDH
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