参数资料
型号: CAT5251WI-50-T1
厂商: ON Semiconductor
文件页数: 15/15页
文件大小: 0K
描述: IC POT DPP 50K 256TAP 24SOIC
标准包装: 1,000
系列: DPP
接片: 256
电阻(欧姆): 50k
电路数: 4
温度系数: 标准值 300 ppm/°C
存储器类型: 非易失
接口: 6 线 SPI(芯片选择,设备位址)
电源电压: 2.5 V ~ 6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-SOIC(0.295",7.50mm 宽)
供应商设备封装: 24-SOIC
包装: 带卷 (TR)
CAT5251
http://onsemi.com
9
Instructions
Four of the ten instructions are three bytes in length. These
instructions are:
Read Wiper Control Register – read the current wiper
position of the selected potentiometer in the WCR
Write Wiper Control Register – change current wiper
position in the WCR of the selected potentiometer
Read Data Register – read the contents of the selected
Data Register
Write Data Register – write a new value to the
selected Data Register
Read Status – Read the status of the WIP bit which
when set to “1” signifies a write cycle is in progress.
Table 13. INSTRUCTION SET (Note: 1/0 = data is one or zero)
Instruction
Instruction Set
Operations
I3
I2
I1
I0
R1
R0
WCR1/P1
WCR0/P0
Read Wiper Control
Register
1
0
1
0
1/0
Read the contents of the Wiper Control Register
pointed to by P1P0
Write Wiper Control
Register
1
0
1
0
1/0
Write new value to the Wiper Control Register
pointed to by P1P0
Read Data Register
1
0
1
1/0
Read the contents of the Data Register pointed to
by P1P0 and R1R0
Write Data Register
1
0
1/0
Write new value to the Data Register pointed to
by P1P0 and R1R0
XFR Data Register
to Wiper Control
Register
1
0
1
1/0
Transfer the contents of the Data Register
pointed to by P1P0 and R1R0 to its
associated Wiper Control Register
XFR Wiper Control
Register to Data
Register
1
0
1/0
Transfer the contents of the Wiper Control
Register pointed to by P1P0 to the Data
Register pointed to by R1R0
Global XFR Data
Registers to Wiper
Control Registers
0
1
1/0
0
Transfer the contents of the Data Registers
pointed to by R1R0 of all four pots to their
respective Wiper Control Registers
Global XFR Wiper
Control Registers to
Data Register
1
0
1/0
0
Transfer the contents of both Wiper Control
Registers to their respective data Registers
pointed to by R1R0 of all four pots
Increment/Decrement
Wiper Control Register
0
1
0
1/0
Enable Increment/decrement of the Control Latch
pointed to by P1P0
Read Status (WIP bit)
0
1
0
1
0
1
Read WIP bit to check internal write cycle status
The basic sequence of the three byte instructions is
illustrated in Figure 7. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper. The
response of the wiper to this action will be delayed by tWRL.
A transfer from the WCR (current wiper position), to a Data
Register is a write to non-volatile memory and takes a
minimum of tWR to complete. The transfer can occur
between one of the four potentiometers and one of its
associated registers; or the transfer can occur between all
potentiometers and one associated register.
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 6. These instructions
transfer data between the host/processor and the CAT5251;
either between the host and one of the data registers or
directly between the host and the Wiper Control Register.
These instructions are:
XFR Data Register to Wiper Control Register
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
XFR Wiper Control Register to Data Register
This transfers the contents of the specified Wiper
Control Register to the specified associated Data
Register.
Global XFR Data Register to Wiper Control
Register
This transfers the contents of all specified Data
Registers to the associated Wiper Control Registers.
Global XFR Wiper Counter Register to Data
Register
This transfers the contents of all Wiper Control Registers
to the specified associated Data Registers.
Increment/Decrement Command
The final command is Increment/Decrement (Figures 8
and 9). The Increment/Decrement command is different
from the other commands. Once the command is issued the
master can clock the selected wiper up and/or down in one
segment steps; thereby providing a fine tuning capability to
the host. For each SCK clock pulse (tHIGH) while SI is
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