参数资料
型号: CAT813VI-GT3
厂商: ON Semiconductor
文件页数: 6/12页
文件大小: 0K
描述: IC SUPERVISOR CIRCUIT 8-SOIC
标准包装: 3,000
类型: 简单复位/加电复位
监视电压数目: 1
输出: 推挽式,图腾柱
复位: 高有效
复位超时: 最小为 140 ms
电压 - 阀值: 4.65V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
CAT705, CAT706, CAT813
TYPICAL PERFORMANCE CHARACTERISTICS
9
8
7
6
5
4
3
2
1.06
1.04
1.02
1.00
0.98
0.96
1
? 40
? 20
0
20
40
60
80
100
120
0.94
? 40
? 20
0
20
40
60
80
100
TEMPERATURE ( ° C)
Figure 2. V CC Supply Current vs. Temperature
TEMPERATURE ( ° C)
Figure 3. Normalized Reset Threshold Voltage
vs. Temperature
FUNCTIONAL DESCRIPTION
Processor Reset
The CAT705, CAT706 & CAT813 detect supply voltage
(V CC ) conditions that are below the specified voltage trip
value (V RST ) and provide a reset output to maintain correct
system operation. On power ? up, RESET (or RESET for the
CAT813) are kept active for a minimum delay t RP of 140 ms
after the supply voltage (V CC ) rises above V RST to allow the
power supply and processor to stabilize. When V CC drops
below the voltage trip value (V RST ), the reset output signals
RESET (or RESET) are pulled active. RESET (or RESET)
is specifically designed to provide the reset input signals for
processors. This provides reliable and consistent operation
Manual Reset
The CAT705, CAT706 & CAT813 each have a Manual
Reset (MR) input to allow for alternative control of the reset
outputs. The MR input is designed for direct connection to
a pushbutton (see Figure 4). The MR input is internally
pulled up by 60 k W resistor and must be pulled low to cause
the reset output to go active. Internally, this input is
debounced and timed such that RESET (or RESET) signals
of at least 140 ms minimum will be generated. The min
140 ms t RP delay commences as the Manual Reset input is
released from the low level. (see Figure 5).
as power is turned on, off or during brownout conditions by
maintaining the processor operation in known conditions.
MR
V CC
GND
PFI
CAT705
CAT706
CAT813
WDO
RESET/RESET
WDI
PFO
Figure 4. Pushbutton RESET
MR
t PDLY
t PB
V IH
V IL
t RP
RESET
V OH
RESET
V OL
Figure 5. Timing Diagram – Pushbutton RESET
http://onsemi.com
6
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