参数资料
型号: CAT885ZI-SA-GT3
厂商: ON Semiconductor
文件页数: 5/8页
文件大小: 0K
描述: IC SUPERVSR 5CH 2.87/1.68V 8MSOP
标准包装: 1
类型: 多压监控器
监视电压数目: 5
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小为 70 ms
电压 - 阀值: 1.68V,2.87V,可调,可调,可调
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: 8-MSOP
包装: 标准包装
其它名称: CAT885ZI-SA-GT3DKR
CAT885
POWER ON RESET (POR)
Applying power to the CAT885 activates a POR circuit
which activates the reset output (active LOW). At
power-up POR prevents the system microprocessor
from starting to operate with insufficient voltage and
prior to stabilization of the clock oscillator. It ensures
that operation is precluded until internal registers are
properly loaded, FPGA’s have downloaded their
configuration data prior and all system power supplies
are above minimum operating levels and stable. The
reset signal remains active until V DD rises above the
minimum preset voltage level for time period t PD .
MANUAL RESET
ˉˉˉ
MR
MR
MR
RST
The manual-reset input (MR ) allows the user to trigger
a reset by using a push-button switch or by
electronically driving the input low. The ˉˉˉ input is an
active LOW debounced input. Reset is asserted
anytime the ˉˉˉ pin is pulled low to less than 100mV
for the minimum ˉˉˉ pulse width or longer. The reset
output remains asserted low for t PD , typically 120ms
and then is released. Figures 2 and 3 illustrate the
CAT885’s operation and ˉˉˉˉ output response times.
V DD/
V DD2
0
MR
V TH1/2
1V
>T PW
0
t PD
t RPD
t PD
t PD
RST
0
t RPD
Figure 2. Power Supply Monitoring Diagram
V MON
V TH
0
t RPD
t PD
RST
0
Figure 3. Auxillary Voltage Monitoring Diagram
? 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
5
Doc. No. MD-3028 Rev. C
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