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参数资料
| 型号： | CBT16213DL |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 通用总线功能 |
| 英文描述： | 24-bit bus exchange switch with 12-bit output enables |
| 中文描述： | CBT/FST/QS/5C/B SERIES, 12-BIT EXCHANGER, TRUE OUTPUT, PDSO56 |
| 封装： | 7.50 MM, PLASTIC, MO-118, SOT-371-1, SSOP-56 |
| 文件页数： | 5/10页 |
| 文件大小： | 76K |
| 代理商： | CBT16213DL |
Philips Semiconductors
Objective specification
CBT16213
24-bit bus exchange switch
with 12-bit output enables
2001 Jan 19
5
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= –40
°
C to +85
°
C
Min
Typ
1
UNIT
Max
V
IK
Input clamp voltage
V
CC
= 4.5 V; I
I
= –18 mA
V
CC
= 0 V; V
I
= 5.5 V
V
CC
= 5.5 V; V
I
= GND or 5.5 V
V
CC
= 5.5 V; I
O
= 0 V, V
I
= V
CC
or GND
V
= 5.5 V, one input at 2.7 V,
other inputs at V
CC
or GND
V
I
= 3 V or 0 V
—
—
–1.2
V
I
I
Input leakage current
—
—
10
μ
A
—
—
±
1
I
CC
Quiescent supply current
2
—
—
3
μ
A
I
CC
Additional supply current per
input pin
2
—
—
2.5
mA
C
I
Control pins
—
4.5
—
pF
C
IO(OFF)
Power-off leakage current,
B port
= 3 V or 0 V; S0 S1 or S2 = V
V
O
= 3 V or 0 V; S0, S1, or S2 = V
CC
—
11.5
—
pF
Power-off leakage current,
A port
—
11.5
—
pF
V
CC
= 4.0 V; V
1
= 2.4 V; I
I
= 15 mA
V
CC
= 4.5 V; V
1
= 0 V; I
I
= 64 mA
V
CC
= 4.5 V; V
1
= 0 V; I
I
= 30 mA
V
CC
= 4.5 V; V
1
= 2.4 V; I
I
= 15 mA
V
CC
= 4.0 V; V
1
= 2.4 V; I
I
= 15 mA
V
CC
= 4.5 V; V
1
= 0 V; I
I
= 64 mA
V
CC
= 4.5 V; V
1
= 0 V; I
I
= 30 mA
V
CC
= 4.5 V; V
1
= 2.4 V; I
I
= 15 mA
—
14
21
A to B or B to A
—
5
7
—
5
7
r
on3
—
8
15
—
22
33
A1 to A2
—
10
14
—
10
14
—
16
22
NOTES:
1. All typical values are at V
= 5 V, T
= 25
°
C
2. This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
3. Measured by the voltage drop between the A and the B terminals at the indicated current through the switch.
On-state resistance is determined by the lowest voltage of the two (A or B) terminals.
AC CHARACTERISTICS
GND = 0 V; t
R;
C
L
= 50 pF
SYMBOL
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
V
CC
= +5.0
V
±
0.5 V
V
CC
= 4.0
V
UNIT
Min
Max
Min
Max
t
pd
Propagation delay
1
A or B
B or A
—
0.25
—
0.25
ns
A1
A2
—
0.5
—
0.5
ns
t
en
Output enable time
to High and Low level
S
A or B
3.2
11.1
—
12.4
ns
S0
A2 and B2
4
10.9
—
13.3
ns
t
dis
Output disable time
from High and Low level
S
A or B
2.3
11.9
—
12.4
ns
S0
A2 and B2
5.7
12
—
12.8
ns
NOTES:
1. This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on-state
resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
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