
2004 Fairchild Semiconductor Corporation
DS005958
www.fairchildsemi.com
October 1987
Revised January 2004
CD402
7BC
Dual
J-
K
Mast
er/
S
lave
Fl
ip-
F
lop
wit
h
Set
a
nd
Reset
CD4027BC
Dual J-K Master/Slave Flip-Flop with Set and Reset
General Description
The CD4027BC dual J-K flip-flops are monolithic comple-
mentary MOS (CMOS) integrated circuits constructed with
N- and P-channel enhancement mode transistors. Each
flip-flop has independent J, K, set, reset, and clock inputs
and buffered Q and Q outputs. These flip-flops are edge
sensitive to the clock input and change state on the posi-
tive-going transition of the clock pulses. Set or reset is
independent of the clock and is accomplished by a high
level on the respective input.
All inputs are protected against damage due to static dis-
charge by diode clamps to VDD and VSS.
Features
s Wide supply voltage range:
3.0V to 15V
s High noise immunity: 0.45 VDD (typ.)
s Low power TTL compatibility: Fan out of 2 driving 74L
or 1 driving 74LS
s Low power: 50 nW (typ.)
s Medium speed operation: 12 MHz (typ.) with 10V
supply
Ordering Code:
Connection Diagram
Top View
Truth Table
I
= HIGH Level
O
= LOW Level
X
= Don’t Care
= LOW-to-HIGH
= HIGH-to-LOW
Note 1: tn1 refers to the time interval prior to the positive clock pulse
transition
Note 2: tn refers to the time intervals after the positive clock pulse
transition
Note 3: Level Change
Order Number
Package Number
Package Description
CD4027BCM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4027BCN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Inputs tn1
(Note 1)
Outputs tn
(Note 2)
CL
(Note 3)
JK
S
R
Q
I
X
OOO
I
O
X
OOO
I
O
O
X
OOO
O
I
XI
O
I
O
I
X
O
X
(No Change)
XX
X
I
O
X
I
O
XX
X
O
I
X
O
I
XX
X
I
X
I