参数资料
型号: CD4040BCSJX
厂商: FAIRCHILD SEMICONDUCTOR CORP
元件分类: 计数器
中文描述: 4000/14000/40000 SERIES, ASYN NEGATIVE EDGE TRIGGERED 12-BIT UP BINARY COUNTER, PDSO16
封装: 5.30 MM, EIAJ TYPE2, SOP-16
文件页数: 5/9页
文件大小: 99K
代理商: CD4040BCSJX
5
www.fairchildsemi.com
CD402
0BC
CD404
0BC
CD406
0BC
AC Electrical Characteristics (Note 4)
CD4020BC, CD4040BC TA = 25°C, CL = 50 pF, RL = 200k, tr = tf = 20 ns, unless otherwise noted
Note 4: AC Parameters are guaranteed by DC correlated testing.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tPHL1, tPLH1
Propagation Delay Time to Q1
VDD = 5V
250
550
ns
VDD = 10V
100
210
VDD = 15V
75
150
tPHL, tPLH
Interstage Propagation Delay Time
VDD = 5V
150
330
ns
from Qn to Qn+1
VDD = 10V
60
125
VDD = 15V
45
90
tTHL, tTLH
Transition Time
VDD = 5V
100
200
ns
VDD = 10V
50
100
VDD = 15V
40
80
tWL, tWH
Minimum Clock Pulse Width
VDD = 5V
125
335
ns
VDD = 10V
50
125
VDD = 15V
40
100
trCL, tfCL
Maximum Clock Rise and Fall Time
VDD = 5V
No Limit
ns
VDD = 10V
No Limit
VDD = 15V
No Limit
fCL
Maximum Clock Frequency
VDD = 5V
1.5
4
MHz
VDD = 10V
4
10
VDD = 15V
5
12
tPHL(R)
Reset Propagation Delay
VDD = 5V
200
450
ns
VDD = 10V
100
210
VDD = 15V
80
170
tWH(R)
Minimum Reset Pulse Width
VDD = 5V
200
450
ns
VDD = 10V
100
210
VDD = 15V
80
170
CIN
Average Input Capacitance
Any Input
5
7.5
pF
CPD
Power Dissipation Capacitance
50
pF
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