参数资料
| 型号： | CD74HC4046ANSR |
| 厂商： | Texas Instruments |
| 文件页数： | 29/34页 |
| 文件大小： | 0K |
| 描述： | IC PLL W/VCO 16SOP |
| 标准包装： | 1 |
| 系列： | 74HC |
| 类型： | 锁相环路（PLL） |
| PLL： | 是 |
| 输入： | CMOS |
| 输出： | CMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:4 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 38MHz |
| 除法器/乘法器： | 无/无 |
| 电源电压： | 2 V ~ 6 V |
| 工作温度： | -55°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.209"，5.30mm 宽） |
| 供应商设备封装： | 16-SO |
| 包装： | 标准包装 |
| 其它名称： | 296-29115-6 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页当前第29页第30页第31页第32页第33页第34页
4
The frequency capture range (2fC) is dened as the
frequency range of input signals on which the PLL will lock if
it was initially out-of-lock. The frequency lock range (2fL)is
dened as the frequency range of input signals on which the
loop will stay locked if it was initially in lock. The capture
range is smaller or equal to the lock range.
With PC1, the capture range depends on the low-pass lter
characteristics and can be made as large as the lock range.
This conguration retains lock behavior even with very noisy
input signals. Typical of this type of phase comparator is that
it can lock to input frequencies close to the harmonics of the
VCO center frequency.
Phase Comparator 2 (PC2)
This is a positive edge-triggered phase and frequency
detector. When the PLL is using this comparator, the loop
is controlled by positive signal transitions and the duty
factors of SIGIN and COMPIN are not important. PC2
comprises two D-type ip-ops, control-gating and a three-
state output stage. The circuit functions as an up-down
counter (Figure 1) where SIGIN causes an up-count and
COMPIN a down-count. The transfer function of PC2,
assuming ripple (fr = fi) is suppressed, is:
VDEMOUT =(VCC/4π)(φSIGIN - φCOMPIN) where
VDEMOUT is the demodulator output at pin 10;
VDEMOUT =VPC2OUT (via low-pass lter).
The average output voltage from PC2, fed to the VCO via the
low-pass lter and seen at the demodulator output at pin 10
(VDEMOUT), is the resultant of the phase differences of
SIGIN and COMPIN as shown in Figure 4. Typical waveforms
for the PC2 loop locked at fo are shown in Figure 5.
When the frequencies of SIGIN and COMPIN are equal but
the phase of SIGIN leads that of COMPIN, the p-type output
driver at PC2OUT is held “ON” for a time corresponding to
the phase difference (
φDEMOUT). When the phase of SIGIN
lags that of COMPIN, the n-type driver is held “ON”.
When the frequency of SIGIN is higher than that of
COMPIN, the p-type output driver is held “ON” for most of
the input signal cycle time, and for the remainder of the
cycle both n- and p-type drivers are “OFF” (three-state). If
the SIGIN frequency is lower than the COMPIN frequency,
then it is the n-type driver that is held “ON” for most of the
cycle. Subsequently, the voltage at the capacitor (C2) of
the low-pass lter connected to PC2OUT varies until the
signal and comparator inputs are equal in both phase and
FIGURE 2. PHASE COMPARATOR 1: AVERAGE OUTPUT
VOLTAGE vs INPUT PHASE DIFFERENCE:
VDEMOUT = VPC1OUT = (VCC/π) (φSIGIN -
φCOMPIN); φDEMOUT =(φSIGIN - φCOMPIN)
VCC
VDEMOUT (AV)
1/2 VCC
0
0o
90o
φ
DEMOUT
180o
FIGURE 3. TYPICAL WAVEFORMS FOR PLL USING PHASE
COMPARATOR 1, LOOP LOCKED AT fo
SIGIN
COMPIN
VCOOUT
PC1OUT
VCOIN
VCC
GND
FIGURE 4. PHASE COMPARATOR 2: AVERAGE OUTPUT
VOLTAGE vs INPUT PHASE DIFFERENCE:
VDEMOUT = VPC2OUT
= (VCC/4π) (φSIGIN - φCOMPIN);
φDEMOUT =(φSIGIN - φCOMPIN)
VCC
VDEMOUT (AV)
1/2 VCC
0
-360o
0o
φ
DEMOUT
360o
FIGURE 5. TYPICAL WAVEFORMS FOR PLL USING PHASE
COMPARATOR 2, LOOP LOCKED AT fo
SIGIN
COMPIN
VCOOUT
PC2OUT
VCOIN
VCC
GND
PCPOUT
HIGH IMPEDANCE OFF - STATE
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
相关PDF资料 |
PDF描述 |
|---|---|
| VE-224-MW-S | CONVERTER MOD DC/DC 48V 100W |
| SY89534LHZ | IC SYNTHESIZR LVPECL OUT 64-TQFP |
| AD9522-0BCPZ | IC CLOCK GEN 2.8GHZ VCO 64LFCSP |
| AD9520-0BCPZ | IC CLOCK GEN 2.8GHZ VCO 64LFCSP |
| AD9522-4BCPZ | IC CLOCK GEN 1.6GHZ VCO 64LFCSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CD74HC4046ANSRE4 | 功能描述:锁相环 - PLL Hi-Spd CMOS Logic PLL RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| CD74HC4046ANSRG4 | 功能描述:锁相环 - PLL Hi Sp CMOS Log Phase Locked-Loop RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| CD74HC4046APW | 功能描述:锁相环 - PLL Hi Sp CMOS Logic Ph-Locked-Loop RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| CD74HC4046APWR | 功能描述:锁相环 - PLL PLL w/ VCO RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| CD74HC4046APWRE4 | 功能描述:锁相环 - PLL Hi-Spd CMOS Logic PLL RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
发布紧急采购，3分钟左右您将得到回复。