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参数资料
| 型号： | CDB4351 |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 13/37页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR CS4351 DAC |
| 标准包装： | 1 |
| 系列： | Popguard® |
| DAC 的数量： | 2 |
| 位数： | 24 |
| 采样率（每秒）： | 192k |
| 数据接口： | 串行 |
| DAC 型： | 电压 |
| 工作温度： | -10°C ~ 70°C |
| 已供物品： | 板，缆线，CD |
| 已用 IC / 零件： | CS4351 |
| 产品目录页面： | 757 (CN2011-ZH PDF) |
| 相关产品： | CS4351-DZZ-ND - IC DAC STER 112DB 192KHZ 20TSSOP 598-1055-5-ND - IC DAC STER 112DB 192KHZ 20TSSOP |
| 其它名称： | 598-1152 |
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20
DS566F1
CS4351
4.9
Control Port Interface
The control port is used to load all the internal register settings (see Section 6). The operation of the control
port may be completely asynchronous with the audio sample rate. However, to avoid potential interference
problems, the control port pins should remain static if no operation is required.
The control port operates in one of two modes: IC or SPI.
4.9.1
MAP Auto Increment
The device has MAP (memory address pointer) auto increment capability enabled by the INCR bit (also
the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive IC writes or reads and
SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or
writes of successive registers.
4.9.2
IC Mode
In the IC mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial
control port clock, SCL (see Figure 9 for the clock to data relationship). There is no CS pin. Pin AD0 en-
ables the user to alter the chip address (100110[AD0][R/W]) and should be tied to VL or GND as required,
before powering up the device. If the device ever detects a high to low transition on the AD0/CS pin after
power-up, SPI mode will be selected.
4.9.2.1
IC Write
To write to the device, follow the procedure below while adhering to the control port Switching Specifica-
tions in Section 8.
1. Initiate a START condition to the IC bus followed by the address byte. The upper 6 bits must be
100110. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth
bit of the address byte is the R/W bit.
2. Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP. This
byte points to the register to be written.
3. Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed to
by the MAP.
4. If the INCR bit (see Section 4.9.1) is set to 1, repeat the previous step until all the desired registers
are written, then initiate a STOP condition to the bus.
5. If the INCR bit is set to 0 and further IC writes to other registers are desired, it is necessary to initiate
a repeated START condition and follow the procedure detailed from step 1. If no further writes to oth-
er registers are desired, initiate a STOP condition to the bus.
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