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参数资料
型号： CDB4382A
厂商： Cirrus Logic Inc
文件页数： 14/50页
文件大小： 0K
描述： BOARD EVAL FOR CS4382A DAC
标准包装： 1
DAC 的数量： 8
位数： 24
采样率（每秒）： 192k
数据接口： 串行
DAC 型： 电压
工作温度： -40°C ~ 85°C
已供物品： 板
已用 IC / 零件： CS4382A
产品目录页面： 757 (CN2011-ZH PDF)
相关产品： CS4382A-DQZR-ND - IC DAC 8CH 114DB 192KHZ 48-LQFP
CS4382A-DQZ-ND - IC DAC 8CH 114DB 192KHZ 48-LQFP
CS4382A-CQZR-ND - IC DAC 8CH 114DB 192KHZ 48-LQFP
598-1061-ND - IC DAC 8CH 114DB 192KHZ 48LQFP
其它名称： 598-1524
DS618F2
21
CS4382A
4. APPLICATIONS
The CS4382A serially accepts two’s-complement formatted PCM data at standard audio sample rates including 48,
44.1, and 32 kHz in SSM, 96, 88.2, and 64 kHz in DSM, and 192, 176.4, and 128 kHz in QSM. Audio data is input
via the serial data input pins (SDINx). The Left/Right Clock (LRCK) determines which channel is currently being input
on SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer.
The CS4382A can be configured in Hardware Mode by the M0, M1, M2, M3, and DSD_EN pins and in Software
Mode through IC or SPI.
4.1
Master Clock
MCLK/LRCK must be an integer ratio as shown in Table 1. The LRCK frequency is equal to Fs, the frequen-
cy at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio is detected
automatically during the initialization sequence by counting the number of MCLK transitions during a single
LRCK period. Internal dividers are then set to generate the proper internal clocks. Table 1 illustrates several
standard audio sample rates and the required MCLK and LRCK frequencies. Please note there is no re-
quired phase relationship, but MCLK, LRCK, and SCLK must be synchronous.
4.2
Mode Select
In Hardware Mode, operation is determined by the Mode Select pins. The states of these pins are continu-
ally scanned for any changes; however, the mode should only be changed while the device is in reset
(RST pin low) to ensure proper switching from one mode to another. These pins require connection to sup-
ply or ground as outlined in Figure 6. VLC supplies M0, M1, and M2. VLS supplies M3 and DSD_EN.
Tables 2 - 4 show the decode of these pins.
In Software Mode, the operational mode and data format are set in the FM and DIF registers. See “Digital
Interface Format (DIF)” on page 34 and “Functional Mode (FM)” on page 40.
Speed Mode
(sample-rate range)
Sample
Rate
(kHz)
MCLK (MHz)
Software
Mode Only
MCLK Ratio
256x
384x
512x
768x
1024x*
Single-Speed
(4 to 50 kHz)
32
8.1920
12.2880
16.3840
24.5760
32.7680
44.1
11.2896
16.9344
22.5792
33.8688
45.1584
48
12.2880
18.4320
24.5760
36.8640
49.1520
MCLK Ratio
128x
192x
256x
384x
512x*
Double-Speed
(50 to 100 kHz)
64
8.1920
12.2880
16.3840
24.5760
32.7680
88.2
11.2896
16.9344
22.5792
33.8688
45.1584
96
12.2880
18.4320
24.5760
36.8640
49.1520
MCLK Ratio
64x
96x
128x
192x
256x*
Quad-Speed
(100 to 200 kHz)
176.4
11.2896
16.9344
22.5792
33.8688
45.1584
192
12.2880
18.4320
24.5760
36.8640
49.1520
Note:
These modes are only available in Software Mode by setting the MCLKDIV bit = 1.
Table 1. Common Clock Frequencies
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