参数资料
型号: CDB4385
厂商: Cirrus Logic Inc
文件页数: 4/32页
文件大小: 0K
描述: BOARD EVAL FOR CS4385 DAC
标准包装: 1
DAC 的数量: 8
位数: 24
采样率(每秒): 192k
数据接口: 串行
DAC 型: 电压
工作温度: -40°C ~ 85°C
已供物品: 板,CD
已用 IC / 零件: CDB4385
产品目录页面: 757 (CN2011-ZH PDF)
相关产品: CS4385-DQZR-ND - IC DAC 8CH 114DB 192KHZ 48-LQFP
CS4385-CQZR-ND - IC DAC 8CH 114DB 192KHZ 48-LQFP
598-1649-ND - IC DAC 8CH 114DB 192KHZ 48LQFP
598-1063-ND - IC DAC 8CH 114DB 192KHZ 48LQFP
其它名称: 598-1154
2
are on the right side. R116 and R119 should be populated with 2-k ? resistors when using an external I C source
CDB4385
CDB4385 SYSTEM OVERVIEW
The CDB4385 evaluation board is an excellent means of quickly evaluating the CS4385. The CS8416 digital audio
interface receiver provides an easy interface to digital audio signal sources including the majority of digital audio test
equipment. The evaluation board also allows the user to supply external PCM or DSD clocks and data through PCB
headers for system development.
The CDB4385 schematic has been partitioned into 10 schematics shown in Figures 44 through 53 . Each partitioned
schematic is represented in the system diagram shown in Figure 43 . Notice that the system diagram also includes
the interconnections between the partitioned schematics.
1. CS4385 DIGITAL-TO-ANALOG CONVERTER
A description of the CS4385 is included in the CS4385 datasheet.
2. CS8416 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard S/PDIF data format using a CS8416 digital audio receiver
( Figure 49 ). The outputs of the CS8416 include a serial bit clock, serial data, left-right clock, and a 128/256 Fs mas-
ter clock. The CS8416 data format is fixed to I S. The operation of the CS8416 and a discussion of the digital audio
interface are included in the CS8416 datasheet.
The evaluation board has been designed such that the input can be either optical or coaxial, see Figure 49 . How-
ever, both inputs cannot be driven simultaneously.
Switch position 7 of S1 sets the output MCLK-to-LRCK ratio of the CS8416. This switch should be set to 256 (closed)
for inputs Fs ≤ 96 kHz and 128 (open) for Fs ≥ 64 kHz. The 8416 must be manually reset using ‘HW RST’ (S2) or
through the software when this switch is changed.
3. INPUT FOR CLOCKS AND DATA
The evaluation board has been designed to allow interfacing to external systems via headers J11 and J7. Header
J11 allows the evaluation board to accept externally generated PCM clocks and data. The schematic for the
clock/data input is shown in Figure 50 . Switch position 6 of S1 selects the source as either CS8416 (open) or header
J11 (closed).
Header J7 allows the evaluation board to accept externally generated DSD data and clocks. The schematic for the
clock/data input is shown in Figure 50 . A synchronous MCLK must still be provided via Header J11. Switch position
8 of S1 selects either PCM (open) or DSD (closed).
Please see the CS4385 datasheet for more information.
4. INPUT FOR CONTROL DATA
The evaluation board can be run in either a stand-alone mode or with a PC. Stand-alone mode uses the CS4385 in
hardware mode and the mode pins are configured using switch positions 1 through 5 of S1. PC mode uses software
to setup the CS4385 through I2C ? using the PC’s serial or USB ports. PC mode is automatically selected when the
serial or USB port is attached and the CDB4385 software is running.
Header J15 offers the option for external input of RST and SPI?/I2C clocks and data. The board is setup from the
factory to use the on-board microcontroller in conjunction with the supplied software. To use an external control
source, remove the shunts on J15 and place a ribbon cable so the signal lines are on the center row and the grounds
2
which does not already provide pull-ups.
4
DS671DB4
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